| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2023, Linaro Limited |
| */ |
| |
| #ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
| #define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_ |
| |
| #define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28 |
| #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c |
| #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 |
| #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 |
| #define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c |
| #define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 |
| |
| #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 |
| #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 |
| #define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28 |
| #define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58 |
| #define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4 |
| #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 |
| #define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc |
| #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 |
| #define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0 |
| #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 |
| #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c |
| #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214 |
| #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220 |
| #define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238 |
| #define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244 |
| #define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c |
| #define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260 |
| #define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264 |
| #define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270 |
| #define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280 |
| #define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c |
| |
| #endif |
