| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA6_QM_REGS_H_ |
| #define ASIC_REG_DMA6_QM_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA6_QM (Prototype: QMAN) |
| ***************************************** |
| */ |
| |
| #define mmDMA6_QM_GLBL_CFG0 0x5C8000 |
| |
| #define mmDMA6_QM_GLBL_CFG1 0x5C8004 |
| |
| #define mmDMA6_QM_GLBL_PROT 0x5C8008 |
| |
| #define mmDMA6_QM_GLBL_ERR_CFG 0x5C800C |
| |
| #define mmDMA6_QM_GLBL_SECURE_PROPS_0 0x5C8010 |
| |
| #define mmDMA6_QM_GLBL_SECURE_PROPS_1 0x5C8014 |
| |
| #define mmDMA6_QM_GLBL_SECURE_PROPS_2 0x5C8018 |
| |
| #define mmDMA6_QM_GLBL_SECURE_PROPS_3 0x5C801C |
| |
| #define mmDMA6_QM_GLBL_SECURE_PROPS_4 0x5C8020 |
| |
| #define mmDMA6_QM_GLBL_NON_SECURE_PROPS_0 0x5C8024 |
| |
| #define mmDMA6_QM_GLBL_NON_SECURE_PROPS_1 0x5C8028 |
| |
| #define mmDMA6_QM_GLBL_NON_SECURE_PROPS_2 0x5C802C |
| |
| #define mmDMA6_QM_GLBL_NON_SECURE_PROPS_3 0x5C8030 |
| |
| #define mmDMA6_QM_GLBL_NON_SECURE_PROPS_4 0x5C8034 |
| |
| #define mmDMA6_QM_GLBL_STS0 0x5C8038 |
| |
| #define mmDMA6_QM_GLBL_STS1_0 0x5C8040 |
| |
| #define mmDMA6_QM_GLBL_STS1_1 0x5C8044 |
| |
| #define mmDMA6_QM_GLBL_STS1_2 0x5C8048 |
| |
| #define mmDMA6_QM_GLBL_STS1_3 0x5C804C |
| |
| #define mmDMA6_QM_GLBL_STS1_4 0x5C8050 |
| |
| #define mmDMA6_QM_GLBL_MSG_EN_0 0x5C8054 |
| |
| #define mmDMA6_QM_GLBL_MSG_EN_1 0x5C8058 |
| |
| #define mmDMA6_QM_GLBL_MSG_EN_2 0x5C805C |
| |
| #define mmDMA6_QM_GLBL_MSG_EN_3 0x5C8060 |
| |
| #define mmDMA6_QM_GLBL_MSG_EN_4 0x5C8068 |
| |
| #define mmDMA6_QM_PQ_BASE_LO_0 0x5C8070 |
| |
| #define mmDMA6_QM_PQ_BASE_LO_1 0x5C8074 |
| |
| #define mmDMA6_QM_PQ_BASE_LO_2 0x5C8078 |
| |
| #define mmDMA6_QM_PQ_BASE_LO_3 0x5C807C |
| |
| #define mmDMA6_QM_PQ_BASE_HI_0 0x5C8080 |
| |
| #define mmDMA6_QM_PQ_BASE_HI_1 0x5C8084 |
| |
| #define mmDMA6_QM_PQ_BASE_HI_2 0x5C8088 |
| |
| #define mmDMA6_QM_PQ_BASE_HI_3 0x5C808C |
| |
| #define mmDMA6_QM_PQ_SIZE_0 0x5C8090 |
| |
| #define mmDMA6_QM_PQ_SIZE_1 0x5C8094 |
| |
| #define mmDMA6_QM_PQ_SIZE_2 0x5C8098 |
| |
| #define mmDMA6_QM_PQ_SIZE_3 0x5C809C |
| |
| #define mmDMA6_QM_PQ_PI_0 0x5C80A0 |
| |
| #define mmDMA6_QM_PQ_PI_1 0x5C80A4 |
| |
| #define mmDMA6_QM_PQ_PI_2 0x5C80A8 |
| |
| #define mmDMA6_QM_PQ_PI_3 0x5C80AC |
| |
| #define mmDMA6_QM_PQ_CI_0 0x5C80B0 |
| |
| #define mmDMA6_QM_PQ_CI_1 0x5C80B4 |
| |
| #define mmDMA6_QM_PQ_CI_2 0x5C80B8 |
| |
| #define mmDMA6_QM_PQ_CI_3 0x5C80BC |
| |
| #define mmDMA6_QM_PQ_CFG0_0 0x5C80C0 |
| |
| #define mmDMA6_QM_PQ_CFG0_1 0x5C80C4 |
| |
| #define mmDMA6_QM_PQ_CFG0_2 0x5C80C8 |
| |
| #define mmDMA6_QM_PQ_CFG0_3 0x5C80CC |
| |
| #define mmDMA6_QM_PQ_CFG1_0 0x5C80D0 |
| |
| #define mmDMA6_QM_PQ_CFG1_1 0x5C80D4 |
| |
| #define mmDMA6_QM_PQ_CFG1_2 0x5C80D8 |
| |
| #define mmDMA6_QM_PQ_CFG1_3 0x5C80DC |
| |
| #define mmDMA6_QM_PQ_ARUSER_31_11_0 0x5C80E0 |
| |
| #define mmDMA6_QM_PQ_ARUSER_31_11_1 0x5C80E4 |
| |
| #define mmDMA6_QM_PQ_ARUSER_31_11_2 0x5C80E8 |
| |
| #define mmDMA6_QM_PQ_ARUSER_31_11_3 0x5C80EC |
| |
| #define mmDMA6_QM_PQ_STS0_0 0x5C80F0 |
| |
| #define mmDMA6_QM_PQ_STS0_1 0x5C80F4 |
| |
| #define mmDMA6_QM_PQ_STS0_2 0x5C80F8 |
| |
| #define mmDMA6_QM_PQ_STS0_3 0x5C80FC |
| |
| #define mmDMA6_QM_PQ_STS1_0 0x5C8100 |
| |
| #define mmDMA6_QM_PQ_STS1_1 0x5C8104 |
| |
| #define mmDMA6_QM_PQ_STS1_2 0x5C8108 |
| |
| #define mmDMA6_QM_PQ_STS1_3 0x5C810C |
| |
| #define mmDMA6_QM_CQ_CFG0_0 0x5C8110 |
| |
| #define mmDMA6_QM_CQ_CFG0_1 0x5C8114 |
| |
| #define mmDMA6_QM_CQ_CFG0_2 0x5C8118 |
| |
| #define mmDMA6_QM_CQ_CFG0_3 0x5C811C |
| |
| #define mmDMA6_QM_CQ_CFG0_4 0x5C8120 |
| |
| #define mmDMA6_QM_CQ_CFG1_0 0x5C8124 |
| |
| #define mmDMA6_QM_CQ_CFG1_1 0x5C8128 |
| |
| #define mmDMA6_QM_CQ_CFG1_2 0x5C812C |
| |
| #define mmDMA6_QM_CQ_CFG1_3 0x5C8130 |
| |
| #define mmDMA6_QM_CQ_CFG1_4 0x5C8134 |
| |
| #define mmDMA6_QM_CQ_ARUSER_31_11_0 0x5C8138 |
| |
| #define mmDMA6_QM_CQ_ARUSER_31_11_1 0x5C813C |
| |
| #define mmDMA6_QM_CQ_ARUSER_31_11_2 0x5C8140 |
| |
| #define mmDMA6_QM_CQ_ARUSER_31_11_3 0x5C8144 |
| |
| #define mmDMA6_QM_CQ_ARUSER_31_11_4 0x5C8148 |
| |
| #define mmDMA6_QM_CQ_STS0_0 0x5C814C |
| |
| #define mmDMA6_QM_CQ_STS0_1 0x5C8150 |
| |
| #define mmDMA6_QM_CQ_STS0_2 0x5C8154 |
| |
| #define mmDMA6_QM_CQ_STS0_3 0x5C8158 |
| |
| #define mmDMA6_QM_CQ_STS0_4 0x5C815C |
| |
| #define mmDMA6_QM_CQ_STS1_0 0x5C8160 |
| |
| #define mmDMA6_QM_CQ_STS1_1 0x5C8164 |
| |
| #define mmDMA6_QM_CQ_STS1_2 0x5C8168 |
| |
| #define mmDMA6_QM_CQ_STS1_3 0x5C816C |
| |
| #define mmDMA6_QM_CQ_STS1_4 0x5C8170 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_0 0x5C8174 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_0 0x5C8178 |
| |
| #define mmDMA6_QM_CQ_TSIZE_0 0x5C817C |
| |
| #define mmDMA6_QM_CQ_CTL_0 0x5C8180 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_1 0x5C8184 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_1 0x5C8188 |
| |
| #define mmDMA6_QM_CQ_TSIZE_1 0x5C818C |
| |
| #define mmDMA6_QM_CQ_CTL_1 0x5C8190 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_2 0x5C8194 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_2 0x5C8198 |
| |
| #define mmDMA6_QM_CQ_TSIZE_2 0x5C819C |
| |
| #define mmDMA6_QM_CQ_CTL_2 0x5C81A0 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_3 0x5C81A4 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_3 0x5C81A8 |
| |
| #define mmDMA6_QM_CQ_TSIZE_3 0x5C81AC |
| |
| #define mmDMA6_QM_CQ_CTL_3 0x5C81B0 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_4 0x5C81B4 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_4 0x5C81B8 |
| |
| #define mmDMA6_QM_CQ_TSIZE_4 0x5C81BC |
| |
| #define mmDMA6_QM_CQ_CTL_4 0x5C81C0 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_STS_0 0x5C81C4 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_STS_1 0x5C81C8 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_STS_2 0x5C81CC |
| |
| #define mmDMA6_QM_CQ_PTR_LO_STS_3 0x5C81D0 |
| |
| #define mmDMA6_QM_CQ_PTR_LO_STS_4 0x5C81D4 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_STS_0 0x5C81D8 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_STS_1 0x5C81DC |
| |
| #define mmDMA6_QM_CQ_PTR_HI_STS_2 0x5C81E0 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_STS_3 0x5C81E4 |
| |
| #define mmDMA6_QM_CQ_PTR_HI_STS_4 0x5C81E8 |
| |
| #define mmDMA6_QM_CQ_TSIZE_STS_0 0x5C81EC |
| |
| #define mmDMA6_QM_CQ_TSIZE_STS_1 0x5C81F0 |
| |
| #define mmDMA6_QM_CQ_TSIZE_STS_2 0x5C81F4 |
| |
| #define mmDMA6_QM_CQ_TSIZE_STS_3 0x5C81F8 |
| |
| #define mmDMA6_QM_CQ_TSIZE_STS_4 0x5C81FC |
| |
| #define mmDMA6_QM_CQ_CTL_STS_0 0x5C8200 |
| |
| #define mmDMA6_QM_CQ_CTL_STS_1 0x5C8204 |
| |
| #define mmDMA6_QM_CQ_CTL_STS_2 0x5C8208 |
| |
| #define mmDMA6_QM_CQ_CTL_STS_3 0x5C820C |
| |
| #define mmDMA6_QM_CQ_CTL_STS_4 0x5C8210 |
| |
| #define mmDMA6_QM_CQ_IFIFO_CNT_0 0x5C8214 |
| |
| #define mmDMA6_QM_CQ_IFIFO_CNT_1 0x5C8218 |
| |
| #define mmDMA6_QM_CQ_IFIFO_CNT_2 0x5C821C |
| |
| #define mmDMA6_QM_CQ_IFIFO_CNT_3 0x5C8220 |
| |
| #define mmDMA6_QM_CQ_IFIFO_CNT_4 0x5C8224 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_0 0x5C8228 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_1 0x5C822C |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_2 0x5C8230 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_3 0x5C8234 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_LO_4 0x5C8238 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_0 0x5C823C |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_1 0x5C8240 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_2 0x5C8244 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_3 0x5C8248 |
| |
| #define mmDMA6_QM_CP_MSG_BASE0_ADDR_HI_4 0x5C824C |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_0 0x5C8250 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_1 0x5C8254 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_2 0x5C8258 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_3 0x5C825C |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_LO_4 0x5C8260 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_0 0x5C8264 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_1 0x5C8268 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_2 0x5C826C |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_3 0x5C8270 |
| |
| #define mmDMA6_QM_CP_MSG_BASE1_ADDR_HI_4 0x5C8274 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_0 0x5C8278 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_1 0x5C827C |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_2 0x5C8280 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_3 0x5C8284 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_LO_4 0x5C8288 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_0 0x5C828C |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_1 0x5C8290 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_2 0x5C8294 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_3 0x5C8298 |
| |
| #define mmDMA6_QM_CP_MSG_BASE2_ADDR_HI_4 0x5C829C |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_0 0x5C82A0 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_1 0x5C82A4 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_2 0x5C82A8 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_3 0x5C82AC |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_LO_4 0x5C82B0 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_0 0x5C82B4 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_1 0x5C82B8 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_2 0x5C82BC |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_3 0x5C82C0 |
| |
| #define mmDMA6_QM_CP_MSG_BASE3_ADDR_HI_4 0x5C82C4 |
| |
| #define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_0 0x5C82C8 |
| |
| #define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_1 0x5C82CC |
| |
| #define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_2 0x5C82D0 |
| |
| #define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_3 0x5C82D4 |
| |
| #define mmDMA6_QM_CP_LDMA_TSIZE_OFFSET_4 0x5C82D8 |
| |
| #define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x5C82E0 |
| |
| #define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x5C82E4 |
| |
| #define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x5C82E8 |
| |
| #define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x5C82EC |
| |
| #define mmDMA6_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x5C82F0 |
| |
| #define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x5C82F4 |
| |
| #define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x5C82F8 |
| |
| #define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x5C82FC |
| |
| #define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x5C8300 |
| |
| #define mmDMA6_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x5C8304 |
| |
| #define mmDMA6_QM_CP_FENCE0_RDATA_0 0x5C8308 |
| |
| #define mmDMA6_QM_CP_FENCE0_RDATA_1 0x5C830C |
| |
| #define mmDMA6_QM_CP_FENCE0_RDATA_2 0x5C8310 |
| |
| #define mmDMA6_QM_CP_FENCE0_RDATA_3 0x5C8314 |
| |
| #define mmDMA6_QM_CP_FENCE0_RDATA_4 0x5C8318 |
| |
| #define mmDMA6_QM_CP_FENCE1_RDATA_0 0x5C831C |
| |
| #define mmDMA6_QM_CP_FENCE1_RDATA_1 0x5C8320 |
| |
| #define mmDMA6_QM_CP_FENCE1_RDATA_2 0x5C8324 |
| |
| #define mmDMA6_QM_CP_FENCE1_RDATA_3 0x5C8328 |
| |
| #define mmDMA6_QM_CP_FENCE1_RDATA_4 0x5C832C |
| |
| #define mmDMA6_QM_CP_FENCE2_RDATA_0 0x5C8330 |
| |
| #define mmDMA6_QM_CP_FENCE2_RDATA_1 0x5C8334 |
| |
| #define mmDMA6_QM_CP_FENCE2_RDATA_2 0x5C8338 |
| |
| #define mmDMA6_QM_CP_FENCE2_RDATA_3 0x5C833C |
| |
| #define mmDMA6_QM_CP_FENCE2_RDATA_4 0x5C8340 |
| |
| #define mmDMA6_QM_CP_FENCE3_RDATA_0 0x5C8344 |
| |
| #define mmDMA6_QM_CP_FENCE3_RDATA_1 0x5C8348 |
| |
| #define mmDMA6_QM_CP_FENCE3_RDATA_2 0x5C834C |
| |
| #define mmDMA6_QM_CP_FENCE3_RDATA_3 0x5C8350 |
| |
| #define mmDMA6_QM_CP_FENCE3_RDATA_4 0x5C8354 |
| |
| #define mmDMA6_QM_CP_FENCE0_CNT_0 0x5C8358 |
| |
| #define mmDMA6_QM_CP_FENCE0_CNT_1 0x5C835C |
| |
| #define mmDMA6_QM_CP_FENCE0_CNT_2 0x5C8360 |
| |
| #define mmDMA6_QM_CP_FENCE0_CNT_3 0x5C8364 |
| |
| #define mmDMA6_QM_CP_FENCE0_CNT_4 0x5C8368 |
| |
| #define mmDMA6_QM_CP_FENCE1_CNT_0 0x5C836C |
| |
| #define mmDMA6_QM_CP_FENCE1_CNT_1 0x5C8370 |
| |
| #define mmDMA6_QM_CP_FENCE1_CNT_2 0x5C8374 |
| |
| #define mmDMA6_QM_CP_FENCE1_CNT_3 0x5C8378 |
| |
| #define mmDMA6_QM_CP_FENCE1_CNT_4 0x5C837C |
| |
| #define mmDMA6_QM_CP_FENCE2_CNT_0 0x5C8380 |
| |
| #define mmDMA6_QM_CP_FENCE2_CNT_1 0x5C8384 |
| |
| #define mmDMA6_QM_CP_FENCE2_CNT_2 0x5C8388 |
| |
| #define mmDMA6_QM_CP_FENCE2_CNT_3 0x5C838C |
| |
| #define mmDMA6_QM_CP_FENCE2_CNT_4 0x5C8390 |
| |
| #define mmDMA6_QM_CP_FENCE3_CNT_0 0x5C8394 |
| |
| #define mmDMA6_QM_CP_FENCE3_CNT_1 0x5C8398 |
| |
| #define mmDMA6_QM_CP_FENCE3_CNT_2 0x5C839C |
| |
| #define mmDMA6_QM_CP_FENCE3_CNT_3 0x5C83A0 |
| |
| #define mmDMA6_QM_CP_FENCE3_CNT_4 0x5C83A4 |
| |
| #define mmDMA6_QM_CP_STS_0 0x5C83A8 |
| |
| #define mmDMA6_QM_CP_STS_1 0x5C83AC |
| |
| #define mmDMA6_QM_CP_STS_2 0x5C83B0 |
| |
| #define mmDMA6_QM_CP_STS_3 0x5C83B4 |
| |
| #define mmDMA6_QM_CP_STS_4 0x5C83B8 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_LO_0 0x5C83BC |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_LO_1 0x5C83C0 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_LO_2 0x5C83C4 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_LO_3 0x5C83C8 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_LO_4 0x5C83CC |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_HI_0 0x5C83D0 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_HI_1 0x5C83D4 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_HI_2 0x5C83D8 |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_HI_3 0x5C83DC |
| |
| #define mmDMA6_QM_CP_CURRENT_INST_HI_4 0x5C83E0 |
| |
| #define mmDMA6_QM_CP_BARRIER_CFG_0 0x5C83F4 |
| |
| #define mmDMA6_QM_CP_BARRIER_CFG_1 0x5C83F8 |
| |
| #define mmDMA6_QM_CP_BARRIER_CFG_2 0x5C83FC |
| |
| #define mmDMA6_QM_CP_BARRIER_CFG_3 0x5C8400 |
| |
| #define mmDMA6_QM_CP_BARRIER_CFG_4 0x5C8404 |
| |
| #define mmDMA6_QM_CP_DBG_0_0 0x5C8408 |
| |
| #define mmDMA6_QM_CP_DBG_0_1 0x5C840C |
| |
| #define mmDMA6_QM_CP_DBG_0_2 0x5C8410 |
| |
| #define mmDMA6_QM_CP_DBG_0_3 0x5C8414 |
| |
| #define mmDMA6_QM_CP_DBG_0_4 0x5C8418 |
| |
| #define mmDMA6_QM_CP_ARUSER_31_11_0 0x5C841C |
| |
| #define mmDMA6_QM_CP_ARUSER_31_11_1 0x5C8420 |
| |
| #define mmDMA6_QM_CP_ARUSER_31_11_2 0x5C8424 |
| |
| #define mmDMA6_QM_CP_ARUSER_31_11_3 0x5C8428 |
| |
| #define mmDMA6_QM_CP_ARUSER_31_11_4 0x5C842C |
| |
| #define mmDMA6_QM_CP_AWUSER_31_11_0 0x5C8430 |
| |
| #define mmDMA6_QM_CP_AWUSER_31_11_1 0x5C8434 |
| |
| #define mmDMA6_QM_CP_AWUSER_31_11_2 0x5C8438 |
| |
| #define mmDMA6_QM_CP_AWUSER_31_11_3 0x5C843C |
| |
| #define mmDMA6_QM_CP_AWUSER_31_11_4 0x5C8440 |
| |
| #define mmDMA6_QM_ARB_CFG_0 0x5C8A00 |
| |
| #define mmDMA6_QM_ARB_CHOISE_Q_PUSH 0x5C8A04 |
| |
| #define mmDMA6_QM_ARB_WRR_WEIGHT_0 0x5C8A08 |
| |
| #define mmDMA6_QM_ARB_WRR_WEIGHT_1 0x5C8A0C |
| |
| #define mmDMA6_QM_ARB_WRR_WEIGHT_2 0x5C8A10 |
| |
| #define mmDMA6_QM_ARB_WRR_WEIGHT_3 0x5C8A14 |
| |
| #define mmDMA6_QM_ARB_CFG_1 0x5C8A18 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_0 0x5C8A20 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_1 0x5C8A24 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_2 0x5C8A28 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_3 0x5C8A2C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_4 0x5C8A30 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_5 0x5C8A34 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_6 0x5C8A38 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_7 0x5C8A3C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_8 0x5C8A40 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_9 0x5C8A44 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_10 0x5C8A48 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_11 0x5C8A4C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_12 0x5C8A50 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_13 0x5C8A54 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_14 0x5C8A58 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_15 0x5C8A5C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_16 0x5C8A60 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_17 0x5C8A64 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_18 0x5C8A68 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_19 0x5C8A6C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_20 0x5C8A70 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_21 0x5C8A74 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_22 0x5C8A78 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_23 0x5C8A7C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_24 0x5C8A80 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_25 0x5C8A84 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_26 0x5C8A88 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_27 0x5C8A8C |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_28 0x5C8A90 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_29 0x5C8A94 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_30 0x5C8A98 |
| |
| #define mmDMA6_QM_ARB_MST_AVAIL_CRED_31 0x5C8A9C |
| |
| #define mmDMA6_QM_ARB_MST_CRED_INC 0x5C8AA0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x5C8AA4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x5C8AA8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x5C8AAC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x5C8AB0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x5C8AB4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x5C8AB8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x5C8ABC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x5C8AC0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x5C8AC4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x5C8AC8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x5C8ACC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x5C8AD0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x5C8AD4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x5C8AD8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x5C8ADC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x5C8AE0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x5C8AE4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x5C8AE8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x5C8AEC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x5C8AF0 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x5C8AF4 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x5C8AF8 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x5C8AFC |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x5C8B00 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x5C8B04 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x5C8B08 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x5C8B0C |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x5C8B10 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x5C8B14 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x5C8B18 |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x5C8B1C |
| |
| #define mmDMA6_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x5C8B20 |
| |
| #define mmDMA6_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x5C8B28 |
| |
| #define mmDMA6_QM_ARB_MST_SLAVE_EN 0x5C8B2C |
| |
| #define mmDMA6_QM_ARB_MST_QUIET_PER 0x5C8B34 |
| |
| #define mmDMA6_QM_ARB_SLV_CHOISE_WDT 0x5C8B38 |
| |
| #define mmDMA6_QM_ARB_SLV_ID 0x5C8B3C |
| |
| #define mmDMA6_QM_ARB_MSG_MAX_INFLIGHT 0x5C8B44 |
| |
| #define mmDMA6_QM_ARB_MSG_AWUSER_31_11 0x5C8B48 |
| |
| #define mmDMA6_QM_ARB_MSG_AWUSER_SEC_PROP 0x5C8B4C |
| |
| #define mmDMA6_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x5C8B50 |
| |
| #define mmDMA6_QM_ARB_BASE_LO 0x5C8B54 |
| |
| #define mmDMA6_QM_ARB_BASE_HI 0x5C8B58 |
| |
| #define mmDMA6_QM_ARB_STATE_STS 0x5C8B80 |
| |
| #define mmDMA6_QM_ARB_CHOISE_FULLNESS_STS 0x5C8B84 |
| |
| #define mmDMA6_QM_ARB_MSG_STS 0x5C8B88 |
| |
| #define mmDMA6_QM_ARB_SLV_CHOISE_Q_HEAD 0x5C8B8C |
| |
| #define mmDMA6_QM_ARB_ERR_CAUSE 0x5C8B9C |
| |
| #define mmDMA6_QM_ARB_ERR_MSG_EN 0x5C8BA0 |
| |
| #define mmDMA6_QM_ARB_ERR_STS_DRP 0x5C8BA8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_0 0x5C8BB0 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_1 0x5C8BB4 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_2 0x5C8BB8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_3 0x5C8BBC |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_4 0x5C8BC0 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_5 0x5C8BC4 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_6 0x5C8BC8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_7 0x5C8BCC |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_8 0x5C8BD0 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_9 0x5C8BD4 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_10 0x5C8BD8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_11 0x5C8BDC |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_12 0x5C8BE0 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_13 0x5C8BE4 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_14 0x5C8BE8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_15 0x5C8BEC |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_16 0x5C8BF0 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_17 0x5C8BF4 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_18 0x5C8BF8 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_19 0x5C8BFC |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_20 0x5C8C00 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_21 0x5C8C04 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_22 0x5C8C08 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_23 0x5C8C0C |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_24 0x5C8C10 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_25 0x5C8C14 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_26 0x5C8C18 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_27 0x5C8C1C |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_28 0x5C8C20 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_29 0x5C8C24 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_30 0x5C8C28 |
| |
| #define mmDMA6_QM_ARB_MST_CRED_STS_31 0x5C8C2C |
| |
| #define mmDMA6_QM_CGM_CFG 0x5C8C70 |
| |
| #define mmDMA6_QM_CGM_STS 0x5C8C74 |
| |
| #define mmDMA6_QM_CGM_CFG1 0x5C8C78 |
| |
| #define mmDMA6_QM_LOCAL_RANGE_BASE 0x5C8C80 |
| |
| #define mmDMA6_QM_LOCAL_RANGE_SIZE 0x5C8C84 |
| |
| #define mmDMA6_QM_CSMR_STRICT_PRIO_CFG 0x5C8C90 |
| |
| #define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_1 0x5C8C94 |
| |
| #define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_0 0x5C8C98 |
| |
| #define mmDMA6_QM_LBW_WR_RATE_LIM_CFG_1 0x5C8C9C |
| |
| #define mmDMA6_QM_HBW_RD_RATE_LIM_CFG_0 0x5C8CA0 |
| |
| #define mmDMA6_QM_GLBL_AXCACHE 0x5C8CA4 |
| |
| #define mmDMA6_QM_IND_GW_APB_CFG 0x5C8CB0 |
| |
| #define mmDMA6_QM_IND_GW_APB_WDATA 0x5C8CB4 |
| |
| #define mmDMA6_QM_IND_GW_APB_RDATA 0x5C8CB8 |
| |
| #define mmDMA6_QM_IND_GW_APB_STATUS 0x5C8CBC |
| |
| #define mmDMA6_QM_GLBL_ERR_ADDR_LO 0x5C8CD0 |
| |
| #define mmDMA6_QM_GLBL_ERR_ADDR_HI 0x5C8CD4 |
| |
| #define mmDMA6_QM_GLBL_ERR_WDATA 0x5C8CD8 |
| |
| #define mmDMA6_QM_GLBL_MEM_INIT_BUSY 0x5C8D00 |
| |
| #endif /* ASIC_REG_DMA6_QM_REGS_H_ */ |
