| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ |
| #define ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA_IF_E_N_DOWN_CH1 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_PERM_SEL 0x4E2108 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_0 0x4E2114 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_1 0x4E2118 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_2 0x4E211C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_3 0x4E2120 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_4 0x4E2124 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_5 0x4E2128 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_6 0x4E212C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_7 0x4E2130 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_8 0x4E2134 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_9 0x4E2138 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_10 0x4E213C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_11 0x4E2140 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_12 0x4E2144 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_13 0x4E2148 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_14 0x4E214C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_15 0x4E2150 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_16 0x4E2154 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_17 0x4E2158 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_18 0x4E215C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_19 0x4E2160 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_20 0x4E2164 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_21 0x4E2168 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_22 0x4E216C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_23 0x4E2170 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_24 0x4E2174 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_25 0x4E2178 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_26 0x4E217C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_HBM_POLY_H3_27 0x4E2180 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_0 0x4E2184 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_1 0x4E2188 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_2 0x4E218C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_3 0x4E2190 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_4 0x4E2194 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_5 0x4E2198 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_6 0x4E219C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_7 0x4E21A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_8 0x4E21A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_9 0x4E21A8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_10 0x4E21AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_11 0x4E21B0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_12 0x4E21B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_13 0x4E21B8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SRAM_POLY_H3_14 0x4E21BC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SCRAM_SRAM_EN 0x4E226C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_EN 0x4E2274 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_SAT 0x4E2278 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_RST 0x4E227C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4E2280 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_SCRAM_HBM_EN 0x4E2284 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_EN 0x4E2288 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_SAT 0x4E228C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_RST 0x4E2290 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4E2294 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_EN 0x4E229C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_SAT 0x4E22A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RST 0x4E22A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4E22AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RL_SRAM_RED 0x4E22B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_EN 0x4E22EC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_EN 0x4E22F0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4E22F4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4E22F8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4E2404 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4E2408 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4E240C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4E2410 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4E2414 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4E2418 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4E241C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4E2420 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4E2424 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4E2428 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4E242C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4E2430 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4E2434 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4E2438 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_0 0x4E2450 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_SEL_1 0x4E2454 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NON_LIN_EN 0x4E2480 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_0 0x4E2500 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_1 0x4E2504 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_2 0x4E2508 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_3 0x4E250C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_BANK_4 0x4E2510 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4E2514 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4E2520 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4E2524 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4E2528 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4E252C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4E2530 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4E2534 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4E2538 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4E253C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4E2540 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4E2550 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4E2554 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4E2558 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4E255C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4E2560 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4E2564 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4E2568 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4E256C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4E2570 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4E2574 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4E2578 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4E257C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4E2580 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4E2584 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4E2588 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4E258C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4E2590 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4E2594 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4E2598 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4E25E4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4E25E8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4E25EC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4E25F0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4E25F4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4E25F8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4E25FC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4E2600 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4E2604 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4E2608 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4E260C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4E2610 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4E2614 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4E2618 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4E261C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4E2620 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4E2624 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4E2628 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4E262C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4E2630 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4E2634 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4E2638 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4E263C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4E2640 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4E2644 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4E2648 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4E264C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4E2650 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4E2654 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4E2658 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4E265C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4E2660 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4E2664 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4E2668 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4E266C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4E2670 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4E2674 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4E2678 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4E267C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4E2680 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4E2684 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4E2688 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4E268C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4E2690 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4E2694 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4E2698 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4E269C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4E26A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4E26A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4E26A8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4E26AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4E26B0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4E26B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4E26B8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4E26BC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4E26C0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4E26C4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4E26C8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4E26CC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4E26D0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4E26D4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4E26D8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4E26DC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4E26E0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4E26E4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4E26E8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4E26EC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4E26F0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4E26F4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4E26F8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4E26FC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4E2700 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4E2704 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4E2708 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4E270C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4E2710 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4E2714 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4E2718 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4E271C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4E2720 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4E2724 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4E2728 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4E272C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4E2730 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4E2734 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4E2738 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4E273C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4E2740 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4E2744 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4E2748 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4E274C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4E2750 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4E2754 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4E2758 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4E275C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4E2760 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4E2764 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4E2768 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4E276C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4E2770 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4E2774 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4E2778 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4E277C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4E2780 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4E2784 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4E2788 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4E278C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4E2790 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4E2794 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4E2798 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4E279C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4E27A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4E27A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4E27A8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4E27AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4E27B0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4E27B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4E27B8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4E27BC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4E27C0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4E27C4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4E27C8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4E27CC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4E27D0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4E27D4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4E27D8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4E27DC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4E27E0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4E2824 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4E2828 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4E282C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4E2830 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4E2834 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4E2838 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4E283C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4E2840 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4E2844 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4E2848 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4E284C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4E2850 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4E2854 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4E2858 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4E285C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4E2860 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4E2864 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4E2868 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4E286C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4E2870 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4E2874 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4E2878 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4E287C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4E2880 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4E2884 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4E2888 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4E288C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4E2890 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4E2894 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4E2898 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4E289C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4E28A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4E28A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4E28A8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4E28AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4E28B0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4E28B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4E28B8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4E28BC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4E28C0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4E28C4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4E28C8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4E28CC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4E28D0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4E28D4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4E28D8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4E28DC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4E28E0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4E28E4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4E28E8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4E28EC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4E28F0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4E28F4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4E28F8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4E28FC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4E2900 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4E2904 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4E2908 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4E290C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4E2910 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4E2914 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4E2918 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4E291C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4E2920 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4E2924 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4E2928 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4E292C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4E2930 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4E2934 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4E2938 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4E293C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4E2940 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4E2944 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4E2948 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4E294C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4E2950 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4E2954 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4E2958 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4E295C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4E2960 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4E2964 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4E2968 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4E296C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4E2970 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4E2974 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4E2978 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4E297C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4E2980 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4E2984 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4E2988 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4E298C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4E2990 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4E2994 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4E2998 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4E299C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4E29A0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4E29A4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4E29A8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4E29AC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4E29B0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4E29B4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4E29B8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4E29BC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4E29C0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4E29C4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4E29C8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4E29CC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4E29D0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4E29D4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4E29D8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4E29DC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4E29E0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4E29E4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4E29E8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4E29EC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4E29F0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4E29F4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4E29F8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4E29FC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4E2A00 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4E2A04 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4E2A08 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4E2A0C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4E2A10 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4E2A14 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4E2A18 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4E2A1C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4E2A20 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4E2A64 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4E2A68 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4E2A6C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4E2A70 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_CFG 0x4E2B64 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_SHIFT 0x4E2B68 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4E2B6C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4E2B70 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4E2B74 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4E2B78 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4E2B7C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4E2B80 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4E2B84 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4E2B88 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_0 0x4E2BAC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_1 0x4E2BB0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_2 0x4E2BB4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_3 0x4E2BB8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_4 0x4E2BBC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_5 0x4E2BC0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_6 0x4E2BC4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_TOKEN_7 0x4E2BC8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_0 0x4E2BEC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_1 0x4E2BF0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_2 0x4E2BF4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_3 0x4E2BF8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_4 0x4E2BFC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_5 0x4E2C00 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_6 0x4E2C04 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_BANK_ID_7 0x4E2C08 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_RGL_WDT 0x4E2C2C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4E2C30 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4E2C34 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4E2C38 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4E2C3C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4E2C40 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4E2C44 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4E2C48 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4E2C4C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4E2C50 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4E2C54 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4E2C58 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4E2C5C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4E2C60 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4E2C64 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4E2C68 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4E2C6C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4E2C70 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4E2C74 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4E2C78 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4E2C7C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4E2C80 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4E2C84 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4E2C88 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4E2C8C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4E2C90 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4E2C94 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4E2C98 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4E2C9C |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4E2CA0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4E2CA4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4E2CA8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4E2CAC |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4E2CB0 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4E2CB4 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4E2CB8 |
| |
| #define mmDMA_IF_E_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4E2CBC |
| |
| #endif /* ASIC_REG_DMA_IF_E_N_DOWN_CH1_REGS_H_ */ |
