| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ |
| #define ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA_IF_E_S_DOWN_CH1 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_PERM_SEL 0x4A2108 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_0 0x4A2114 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_1 0x4A2118 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_2 0x4A211C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_3 0x4A2120 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_4 0x4A2124 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_5 0x4A2128 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_6 0x4A212C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_7 0x4A2130 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_8 0x4A2134 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_9 0x4A2138 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_10 0x4A213C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_11 0x4A2140 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_12 0x4A2144 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_13 0x4A2148 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_14 0x4A214C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_15 0x4A2150 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_16 0x4A2154 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_17 0x4A2158 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_18 0x4A215C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_19 0x4A2160 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_20 0x4A2164 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_21 0x4A2168 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_22 0x4A216C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_23 0x4A2170 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_24 0x4A2174 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_25 0x4A2178 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_26 0x4A217C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_HBM_POLY_H3_27 0x4A2180 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_0 0x4A2184 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_1 0x4A2188 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_2 0x4A218C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_3 0x4A2190 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_4 0x4A2194 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_5 0x4A2198 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_6 0x4A219C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_7 0x4A21A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_8 0x4A21A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_9 0x4A21A8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_10 0x4A21AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_11 0x4A21B0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_12 0x4A21B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_13 0x4A21B8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SRAM_POLY_H3_14 0x4A21BC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SCRAM_SRAM_EN 0x4A226C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_EN 0x4A2274 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_SAT 0x4A2278 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_RST 0x4A227C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_HBM_TIMEOUT 0x4A2280 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_SCRAM_HBM_EN 0x4A2284 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_EN 0x4A2288 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_SAT 0x4A228C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_RST 0x4A2290 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_PCI_TIMEOUT 0x4A2294 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_EN 0x4A229C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_SAT 0x4A22A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RST 0x4A22A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_TIMEOUT 0x4A22AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RL_SRAM_RED 0x4A22B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_EN 0x4A22EC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_EN 0x4A22F0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_WR_SIZE 0x4A22F4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_WR_SIZE 0x4A22F8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4A2404 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4A2408 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4A240C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4A2410 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4A2414 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4A2418 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_HBM_RD_SIZE 0x4A241C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_PCI_RD_SIZE 0x4A2420 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4A2424 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4A2428 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4A242C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4A2430 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4A2434 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4A2438 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_0 0x4A2450 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_SEL_1 0x4A2454 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NON_LIN_EN 0x4A2480 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_0 0x4A2500 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_1 0x4A2504 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_2 0x4A2508 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_3 0x4A250C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_BANK_4 0x4A2510 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_0 0x4A2514 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_1 0x4A2520 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_2 0x4A2524 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_3 0x4A2528 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_4 0x4A252C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_5 0x4A2530 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_6 0x4A2534 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_7 0x4A2538 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_8 0x4A253C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_SRAM_OFFSET_9 0x4A2540 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_0 0x4A2550 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_1 0x4A2554 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_2 0x4A2558 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_3 0x4A255C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_4 0x4A2560 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_5 0x4A2564 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_6 0x4A2568 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_7 0x4A256C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_8 0x4A2570 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_9 0x4A2574 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_10 0x4A2578 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_11 0x4A257C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_12 0x4A2580 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_13 0x4A2584 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_14 0x4A2588 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_15 0x4A258C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_16 0x4A2590 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_17 0x4A2594 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_OFFSET_18 0x4A2598 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4A25E4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4A25E8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4A25EC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4A25F0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4A25F4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4A25F8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4A25FC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4A2600 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4A2604 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4A2608 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4A260C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4A2610 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4A2614 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4A2618 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4A261C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4A2620 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4A2624 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4A2628 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4A262C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4A2630 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4A2634 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4A2638 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4A263C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4A2640 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4A2644 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4A2648 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4A264C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4A2650 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4A2654 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4A2658 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4A265C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4A2660 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4A2664 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4A2668 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4A266C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4A2670 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4A2674 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4A2678 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4A267C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4A2680 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4A2684 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4A2688 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4A268C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4A2690 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4A2694 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4A2698 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4A269C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4A26A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4A26A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4A26A8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4A26AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4A26B0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4A26B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4A26B8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4A26BC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4A26C0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4A26C4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4A26C8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4A26CC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4A26D0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4A26D4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4A26D8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4A26DC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4A26E0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4A26E4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4A26E8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4A26EC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4A26F0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4A26F4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4A26F8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4A26FC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4A2700 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4A2704 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4A2708 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4A270C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4A2710 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4A2714 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4A2718 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4A271C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4A2720 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4A2724 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4A2728 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4A272C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4A2730 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4A2734 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4A2738 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4A273C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4A2740 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4A2744 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4A2748 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4A274C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4A2750 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4A2754 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4A2758 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4A275C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4A2760 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4A2764 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4A2768 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4A276C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4A2770 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4A2774 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4A2778 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4A277C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4A2780 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4A2784 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4A2788 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4A278C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4A2790 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4A2794 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4A2798 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4A279C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4A27A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4A27A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4A27A8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4A27AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4A27B0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4A27B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4A27B8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4A27BC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4A27C0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4A27C4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4A27C8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4A27CC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4A27D0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4A27D4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4A27D8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4A27DC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4A27E0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4A2824 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4A2828 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4A282C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4A2830 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4A2834 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4A2838 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4A283C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4A2840 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4A2844 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4A2848 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4A284C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4A2850 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4A2854 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4A2858 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4A285C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4A2860 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4A2864 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4A2868 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4A286C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4A2870 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4A2874 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4A2878 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4A287C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4A2880 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4A2884 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4A2888 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4A288C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4A2890 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4A2894 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4A2898 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4A289C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4A28A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4A28A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4A28A8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4A28AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4A28B0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4A28B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4A28B8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4A28BC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4A28C0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4A28C4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4A28C8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4A28CC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4A28D0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4A28D4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4A28D8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4A28DC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4A28E0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4A28E4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4A28E8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4A28EC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4A28F0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4A28F4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4A28F8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4A28FC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4A2900 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4A2904 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4A2908 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4A290C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4A2910 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4A2914 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4A2918 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4A291C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4A2920 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4A2924 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4A2928 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4A292C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4A2930 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4A2934 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4A2938 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4A293C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4A2940 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4A2944 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4A2948 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4A294C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4A2950 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4A2954 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4A2958 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4A295C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4A2960 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4A2964 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4A2968 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4A296C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4A2970 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4A2974 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4A2978 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4A297C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4A2980 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4A2984 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4A2988 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4A298C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4A2990 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4A2994 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4A2998 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4A299C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4A29A0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4A29A4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4A29A8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4A29AC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4A29B0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4A29B4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4A29B8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4A29BC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4A29C0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4A29C4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4A29C8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4A29CC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4A29D0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4A29D4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4A29D8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4A29DC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4A29E0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4A29E4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4A29E8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4A29EC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4A29F0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4A29F4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4A29F8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4A29FC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4A2A00 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4A2A04 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4A2A08 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4A2A0C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4A2A10 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4A2A14 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4A2A18 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4A2A1C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4A2A20 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AW 0x4A2A64 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_SEC_HIT_AR 0x4A2A68 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4A2A6C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4A2A70 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_CFG 0x4A2B64 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_SHIFT 0x4A2B68 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4A2B6C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4A2B70 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4A2B74 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4A2B78 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4A2B7C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4A2B80 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4A2B84 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4A2B88 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_0 0x4A2BAC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_1 0x4A2BB0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_2 0x4A2BB4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_3 0x4A2BB8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_4 0x4A2BBC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_5 0x4A2BC0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_6 0x4A2BC4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_TOKEN_7 0x4A2BC8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_0 0x4A2BEC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_1 0x4A2BF0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_2 0x4A2BF4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_3 0x4A2BF8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_4 0x4A2BFC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_5 0x4A2C00 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_6 0x4A2C04 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_BANK_ID_7 0x4A2C08 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_RGL_WDT 0x4A2C2C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4A2C30 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4A2C34 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4A2C38 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4A2C3C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4A2C40 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4A2C44 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4A2C48 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4A2C4C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4A2C50 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4A2C54 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4A2C58 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4A2C5C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4A2C60 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4A2C64 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4A2C68 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4A2C6C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4A2C70 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4A2C74 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4A2C78 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4A2C7C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4A2C80 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4A2C84 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4A2C88 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4A2C8C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4A2C90 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4A2C94 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4A2C98 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4A2C9C |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4A2CA0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4A2CA4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4A2CA8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4A2CAC |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_0 0x4A2CB0 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_1 0x4A2CB4 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_2 0x4A2CB8 |
| |
| #define mmDMA_IF_E_S_DOWN_CH1_NL_HBM_PC_SEL_3 0x4A2CBC |
| |
| #endif /* ASIC_REG_DMA_IF_E_S_DOWN_CH1_REGS_H_ */ |
