| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ |
| #define ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA_IF_W_N_DOWN_CH1 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_PERM_SEL 0x4C2108 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_0 0x4C2114 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_1 0x4C2118 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_2 0x4C211C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_3 0x4C2120 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_4 0x4C2124 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_5 0x4C2128 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_6 0x4C212C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_7 0x4C2130 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_8 0x4C2134 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_9 0x4C2138 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_10 0x4C213C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_11 0x4C2140 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_12 0x4C2144 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_13 0x4C2148 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_14 0x4C214C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_15 0x4C2150 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_16 0x4C2154 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_17 0x4C2158 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_18 0x4C215C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_19 0x4C2160 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_20 0x4C2164 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_21 0x4C2168 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_22 0x4C216C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_23 0x4C2170 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_24 0x4C2174 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_25 0x4C2178 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_26 0x4C217C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_HBM_POLY_H3_27 0x4C2180 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_0 0x4C2184 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_1 0x4C2188 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_2 0x4C218C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_3 0x4C2190 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_4 0x4C2194 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_5 0x4C2198 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_6 0x4C219C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_7 0x4C21A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_8 0x4C21A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_9 0x4C21A8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_10 0x4C21AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_11 0x4C21B0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_12 0x4C21B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_13 0x4C21B8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SRAM_POLY_H3_14 0x4C21BC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SCRAM_SRAM_EN 0x4C226C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_EN 0x4C2274 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_SAT 0x4C2278 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_RST 0x4C227C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_HBM_TIMEOUT 0x4C2280 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_SCRAM_HBM_EN 0x4C2284 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_EN 0x4C2288 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_SAT 0x4C228C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_RST 0x4C2290 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_PCI_TIMEOUT 0x4C2294 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_EN 0x4C229C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_SAT 0x4C22A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RST 0x4C22A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_TIMEOUT 0x4C22AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RL_SRAM_RED 0x4C22B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_EN 0x4C22EC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_EN 0x4C22F0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_WR_SIZE 0x4C22F4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_WR_SIZE 0x4C22F8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET_EN 0x4C2404 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_SET 0x4C2408 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_WRAP 0x4C240C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_PCI_CTR_CNT 0x4C2410 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET_EN 0x4C2414 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM_CTR_SET 0x4C2418 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_HBM_RD_SIZE 0x4C241C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_PCI_RD_SIZE 0x4C2420 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET_EN 0x4C2424 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_SET 0x4C2428 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_WRAP 0x4C242C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_PCI_CTR_CNT 0x4C2430 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET_EN 0x4C2434 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM_CTR_SET 0x4C2438 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_0 0x4C2450 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_SEL_1 0x4C2454 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NON_LIN_EN 0x4C2480 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_0 0x4C2500 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_1 0x4C2504 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_2 0x4C2508 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_3 0x4C250C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_BANK_4 0x4C2510 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_0 0x4C2514 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_1 0x4C2520 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_2 0x4C2524 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_3 0x4C2528 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_4 0x4C252C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_5 0x4C2530 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_6 0x4C2534 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_7 0x4C2538 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_8 0x4C253C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_SRAM_OFFSET_9 0x4C2540 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_0 0x4C2550 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_1 0x4C2554 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_2 0x4C2558 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_3 0x4C255C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_4 0x4C2560 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_5 0x4C2564 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_6 0x4C2568 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_7 0x4C256C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_8 0x4C2570 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_9 0x4C2574 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_10 0x4C2578 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_11 0x4C257C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_12 0x4C2580 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_13 0x4C2584 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_14 0x4C2588 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_15 0x4C258C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_16 0x4C2590 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_17 0x4C2594 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_OFFSET_18 0x4C2598 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_0 0x4C25E4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_1 0x4C25E8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_2 0x4C25EC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_3 0x4C25F0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_4 0x4C25F4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_5 0x4C25F8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_6 0x4C25FC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_7 0x4C2600 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_8 0x4C2604 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_9 0x4C2608 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_10 0x4C260C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_11 0x4C2610 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_12 0x4C2614 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_13 0x4C2618 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_14 0x4C261C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AW_15 0x4C2620 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_0 0x4C2624 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_1 0x4C2628 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_2 0x4C262C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_3 0x4C2630 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_4 0x4C2634 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_5 0x4C2638 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_6 0x4C263C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_7 0x4C2640 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_8 0x4C2644 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_9 0x4C2648 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_10 0x4C264C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_11 0x4C2650 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_12 0x4C2654 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_13 0x4C2658 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_14 0x4C265C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AW_15 0x4C2660 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_0 0x4C2664 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_1 0x4C2668 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_2 0x4C266C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_3 0x4C2670 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_4 0x4C2674 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_5 0x4C2678 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_6 0x4C267C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_7 0x4C2680 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_8 0x4C2684 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_9 0x4C2688 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_10 0x4C268C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_11 0x4C2690 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_12 0x4C2694 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_13 0x4C2698 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_14 0x4C269C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AW_15 0x4C26A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_0 0x4C26A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_1 0x4C26A8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_2 0x4C26AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_3 0x4C26B0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_4 0x4C26B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_5 0x4C26B8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_6 0x4C26BC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_7 0x4C26C0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_8 0x4C26C4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_9 0x4C26C8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_10 0x4C26CC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_11 0x4C26D0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_12 0x4C26D4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_13 0x4C26D8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_14 0x4C26DC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AW_15 0x4C26E0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_0 0x4C26E4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_1 0x4C26E8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_2 0x4C26EC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_3 0x4C26F0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_4 0x4C26F4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_5 0x4C26F8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_6 0x4C26FC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_7 0x4C2700 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_8 0x4C2704 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_9 0x4C2708 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_10 0x4C270C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_11 0x4C2710 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_12 0x4C2714 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_13 0x4C2718 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_14 0x4C271C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AW_15 0x4C2720 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_0 0x4C2724 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_1 0x4C2728 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_2 0x4C272C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_3 0x4C2730 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_4 0x4C2734 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_5 0x4C2738 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_6 0x4C273C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_7 0x4C2740 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_8 0x4C2744 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_9 0x4C2748 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_10 0x4C274C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_11 0x4C2750 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_12 0x4C2754 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_13 0x4C2758 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_14 0x4C275C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AW_15 0x4C2760 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_0 0x4C2764 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_1 0x4C2768 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_2 0x4C276C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_3 0x4C2770 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_4 0x4C2774 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_5 0x4C2778 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_6 0x4C277C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_7 0x4C2780 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_8 0x4C2784 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_9 0x4C2788 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_10 0x4C278C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_11 0x4C2790 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_12 0x4C2794 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_13 0x4C2798 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_14 0x4C279C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AW_15 0x4C27A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_0 0x4C27A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_1 0x4C27A8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_2 0x4C27AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_3 0x4C27B0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_4 0x4C27B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_5 0x4C27B8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_6 0x4C27BC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_7 0x4C27C0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_8 0x4C27C4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_9 0x4C27C8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_10 0x4C27CC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_11 0x4C27D0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_12 0x4C27D4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_13 0x4C27D8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_14 0x4C27DC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AW_15 0x4C27E0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_0 0x4C2824 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_1 0x4C2828 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_2 0x4C282C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_3 0x4C2830 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_4 0x4C2834 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_5 0x4C2838 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_6 0x4C283C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_7 0x4C2840 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_8 0x4C2844 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_9 0x4C2848 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_10 0x4C284C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_11 0x4C2850 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_12 0x4C2854 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_13 0x4C2858 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_14 0x4C285C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_LOW_AR_15 0x4C2860 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_0 0x4C2864 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_1 0x4C2868 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_2 0x4C286C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_3 0x4C2870 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_4 0x4C2874 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_5 0x4C2878 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_6 0x4C287C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_7 0x4C2880 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_8 0x4C2884 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_9 0x4C2888 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_10 0x4C288C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_11 0x4C2890 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_12 0x4C2894 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_13 0x4C2898 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_14 0x4C289C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_BASE_HIGH_AR_15 0x4C28A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_0 0x4C28A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_1 0x4C28A8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_2 0x4C28AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_3 0x4C28B0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_4 0x4C28B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_5 0x4C28B8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_6 0x4C28BC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_7 0x4C28C0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_8 0x4C28C4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_9 0x4C28C8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_10 0x4C28CC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_11 0x4C28D0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_12 0x4C28D4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_13 0x4C28D8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_14 0x4C28DC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_LOW_AR_15 0x4C28E0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_0 0x4C28E4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_1 0x4C28E8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_2 0x4C28EC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_3 0x4C28F0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_4 0x4C28F4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_5 0x4C28F8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_6 0x4C28FC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_7 0x4C2900 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_8 0x4C2904 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_9 0x4C2908 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_10 0x4C290C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_11 0x4C2910 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_12 0x4C2914 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_13 0x4C2918 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_14 0x4C291C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_MASK_HIGH_AR_15 0x4C2920 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_0 0x4C2924 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_1 0x4C2928 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_2 0x4C292C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_3 0x4C2930 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_4 0x4C2934 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_5 0x4C2938 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_6 0x4C293C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_7 0x4C2940 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_8 0x4C2944 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_9 0x4C2948 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_10 0x4C294C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_11 0x4C2950 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_12 0x4C2954 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_13 0x4C2958 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_14 0x4C295C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_LOW_AR_15 0x4C2960 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_0 0x4C2964 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_1 0x4C2968 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_2 0x4C296C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_3 0x4C2970 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_4 0x4C2974 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_5 0x4C2978 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_6 0x4C297C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_7 0x4C2980 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_8 0x4C2984 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_9 0x4C2988 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_10 0x4C298C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_11 0x4C2990 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_12 0x4C2994 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_13 0x4C2998 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_14 0x4C299C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_BASE_HIGH_AR_15 0x4C29A0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_0 0x4C29A4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_1 0x4C29A8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_2 0x4C29AC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_3 0x4C29B0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_4 0x4C29B4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_5 0x4C29B8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_6 0x4C29BC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_7 0x4C29C0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_8 0x4C29C4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_9 0x4C29C8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_10 0x4C29CC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_11 0x4C29D0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_12 0x4C29D4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_13 0x4C29D8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_14 0x4C29DC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_LOW_AR_15 0x4C29E0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_0 0x4C29E4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_1 0x4C29E8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_2 0x4C29EC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_3 0x4C29F0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_4 0x4C29F4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_5 0x4C29F8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_6 0x4C29FC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_7 0x4C2A00 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_8 0x4C2A04 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_9 0x4C2A08 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_10 0x4C2A0C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_11 0x4C2A10 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_12 0x4C2A14 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_13 0x4C2A18 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_14 0x4C2A1C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_MASK_HIGH_AR_15 0x4C2A20 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AW 0x4C2A64 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_SEC_HIT_AR 0x4C2A68 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AW 0x4C2A6C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RANGE_PRIV_HIT_AR 0x4C2A70 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_CFG 0x4C2B64 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_SHIFT 0x4C2B68 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_0 0x4C2B6C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_1 0x4C2B70 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_2 0x4C2B74 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_3 0x4C2B78 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_4 0x4C2B7C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_5 0x4C2B80 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_6 0x4C2B84 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_EXPECTED_LAT_7 0x4C2B88 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_0 0x4C2BAC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_1 0x4C2BB0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_2 0x4C2BB4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_3 0x4C2BB8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_4 0x4C2BBC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_5 0x4C2BC0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_6 0x4C2BC4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_TOKEN_7 0x4C2BC8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_0 0x4C2BEC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_1 0x4C2BF0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_2 0x4C2BF4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_3 0x4C2BF8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_4 0x4C2BFC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_5 0x4C2C00 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_6 0x4C2C04 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_BANK_ID_7 0x4C2C08 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_RGL_WDT 0x4C2C2C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_WRAP 0x4C2C30 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_WRAP 0x4C2C34 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_WRAP 0x4C2C38 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_WRAP 0x4C2C3C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_WRAP 0x4C2C40 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_WRAP 0x4C2C44 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_WRAP 0x4C2C48 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_WRAP 0x4C2C4C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH0_CTR_CNT 0x4C2C50 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM0_CH1_CTR_CNT 0x4C2C54 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH0_CTR_CNT 0x4C2C58 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM1_CH1_CTR_CNT 0x4C2C5C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH0_CTR_CNT 0x4C2C60 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM2_CH1_CTR_CNT 0x4C2C64 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH0_CTR_CNT 0x4C2C68 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AR_HBM3_CH1_CTR_CNT 0x4C2C6C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_WRAP 0x4C2C70 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_WRAP 0x4C2C74 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_WRAP 0x4C2C78 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_WRAP 0x4C2C7C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_WRAP 0x4C2C80 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_WRAP 0x4C2C84 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_WRAP 0x4C2C88 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_WRAP 0x4C2C8C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH0_CTR_CNT 0x4C2C90 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM0_CH1_CTR_CNT 0x4C2C94 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH0_CTR_CNT 0x4C2C98 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM1_CH1_CTR_CNT 0x4C2C9C |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH0_CTR_CNT 0x4C2CA0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM2_CH1_CTR_CNT 0x4C2CA4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH0_CTR_CNT 0x4C2CA8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_E2E_AW_HBM3_CH1_CTR_CNT 0x4C2CAC |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_0 0x4C2CB0 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_1 0x4C2CB4 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_2 0x4C2CB8 |
| |
| #define mmDMA_IF_W_N_DOWN_CH1_NL_HBM_PC_SEL_3 0x4C2CBC |
| |
| #endif /* ASIC_REG_DMA_IF_W_N_DOWN_CH1_REGS_H_ */ |
