| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ |
| #define ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ |
| |
| /* |
| ***************************************** |
| * DMA_IF_W_S_DOWN_CH0 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_PERM_SEL 0x481108 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_0 0x481114 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_1 0x481118 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_2 0x48111C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_3 0x481120 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_4 0x481124 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_5 0x481128 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_6 0x48112C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_7 0x481130 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_8 0x481134 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_9 0x481138 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_10 0x48113C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_11 0x481140 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_12 0x481144 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_13 0x481148 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_14 0x48114C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_15 0x481150 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_16 0x481154 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_17 0x481158 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_18 0x48115C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_19 0x481160 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_20 0x481164 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_21 0x481168 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_22 0x48116C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_23 0x481170 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_24 0x481174 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_25 0x481178 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_26 0x48117C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_HBM_POLY_H3_27 0x481180 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_0 0x481184 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_1 0x481188 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_2 0x48118C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_3 0x481190 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_4 0x481194 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_5 0x481198 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_6 0x48119C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_7 0x4811A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_8 0x4811A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_9 0x4811A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_10 0x4811AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_11 0x4811B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_12 0x4811B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_13 0x4811B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SRAM_POLY_H3_14 0x4811BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SCRAM_SRAM_EN 0x48126C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_EN 0x481274 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_SAT 0x481278 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_RST 0x48127C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_HBM_TIMEOUT 0x481280 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_SCRAM_HBM_EN 0x481284 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_EN 0x481288 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_SAT 0x48128C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_RST 0x481290 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_PCI_TIMEOUT 0x481294 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_EN 0x48129C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_SAT 0x4812A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RST 0x4812A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_TIMEOUT 0x4812AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RL_SRAM_RED 0x4812B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_EN 0x4812EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_EN 0x4812F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_WR_SIZE 0x4812F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_WR_SIZE 0x4812F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET_EN 0x481404 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_SET 0x481408 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_WRAP 0x48140C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_PCI_CTR_CNT 0x481410 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET_EN 0x481414 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM_CTR_SET 0x481418 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_HBM_RD_SIZE 0x48141C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_PCI_RD_SIZE 0x481420 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET_EN 0x481424 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_SET 0x481428 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_WRAP 0x48142C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_PCI_CTR_CNT 0x481430 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET_EN 0x481434 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM_CTR_SET 0x481438 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_0 0x481450 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_SEL_1 0x481454 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NON_LIN_EN 0x481480 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_0 0x481500 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_1 0x481504 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_2 0x481508 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_3 0x48150C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_BANK_4 0x481510 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_0 0x481514 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_1 0x481520 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_2 0x481524 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_3 0x481528 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_4 0x48152C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_5 0x481530 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_6 0x481534 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_7 0x481538 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_8 0x48153C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_SRAM_OFFSET_9 0x481540 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_0 0x481550 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_1 0x481554 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_2 0x481558 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_3 0x48155C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_4 0x481560 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_5 0x481564 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_6 0x481568 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_7 0x48156C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_8 0x481570 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_9 0x481574 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_10 0x481578 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_11 0x48157C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_12 0x481580 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_13 0x481584 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_14 0x481588 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_15 0x48158C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_16 0x481590 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_17 0x481594 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_OFFSET_18 0x481598 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_0 0x4815E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_1 0x4815E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_2 0x4815EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_3 0x4815F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_4 0x4815F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_5 0x4815F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_6 0x4815FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_7 0x481600 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_8 0x481604 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_9 0x481608 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_10 0x48160C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_11 0x481610 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_12 0x481614 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_13 0x481618 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_14 0x48161C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AW_15 0x481620 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_0 0x481624 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_1 0x481628 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_2 0x48162C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_3 0x481630 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_4 0x481634 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_5 0x481638 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_6 0x48163C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_7 0x481640 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_8 0x481644 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_9 0x481648 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_10 0x48164C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_11 0x481650 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_12 0x481654 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_13 0x481658 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_14 0x48165C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AW_15 0x481660 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_0 0x481664 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_1 0x481668 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_2 0x48166C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_3 0x481670 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_4 0x481674 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_5 0x481678 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_6 0x48167C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_7 0x481680 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_8 0x481684 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_9 0x481688 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_10 0x48168C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_11 0x481690 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_12 0x481694 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_13 0x481698 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_14 0x48169C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AW_15 0x4816A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_0 0x4816A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_1 0x4816A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_2 0x4816AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_3 0x4816B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_4 0x4816B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_5 0x4816B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_6 0x4816BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_7 0x4816C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_8 0x4816C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_9 0x4816C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_10 0x4816CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_11 0x4816D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_12 0x4816D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_13 0x4816D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_14 0x4816DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AW_15 0x4816E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_0 0x4816E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_1 0x4816E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_2 0x4816EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_3 0x4816F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_4 0x4816F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_5 0x4816F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_6 0x4816FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_7 0x481700 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_8 0x481704 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_9 0x481708 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_10 0x48170C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_11 0x481710 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_12 0x481714 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_13 0x481718 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_14 0x48171C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AW_15 0x481720 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_0 0x481724 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_1 0x481728 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_2 0x48172C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_3 0x481730 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_4 0x481734 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_5 0x481738 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_6 0x48173C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_7 0x481740 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_8 0x481744 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_9 0x481748 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_10 0x48174C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_11 0x481750 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_12 0x481754 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_13 0x481758 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_14 0x48175C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AW_15 0x481760 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_0 0x481764 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_1 0x481768 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_2 0x48176C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_3 0x481770 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_4 0x481774 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_5 0x481778 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_6 0x48177C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_7 0x481780 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_8 0x481784 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_9 0x481788 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_10 0x48178C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_11 0x481790 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_12 0x481794 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_13 0x481798 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_14 0x48179C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AW_15 0x4817A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_0 0x4817A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_1 0x4817A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_2 0x4817AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_3 0x4817B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_4 0x4817B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_5 0x4817B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_6 0x4817BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_7 0x4817C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_8 0x4817C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_9 0x4817C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_10 0x4817CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_11 0x4817D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_12 0x4817D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_13 0x4817D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_14 0x4817DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AW_15 0x4817E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_0 0x481824 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_1 0x481828 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_2 0x48182C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_3 0x481830 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_4 0x481834 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_5 0x481838 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_6 0x48183C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_7 0x481840 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_8 0x481844 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_9 0x481848 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_10 0x48184C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_11 0x481850 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_12 0x481854 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_13 0x481858 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_14 0x48185C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_LOW_AR_15 0x481860 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_0 0x481864 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_1 0x481868 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_2 0x48186C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_3 0x481870 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_4 0x481874 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_5 0x481878 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_6 0x48187C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_7 0x481880 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_8 0x481884 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_9 0x481888 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_10 0x48188C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_11 0x481890 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_12 0x481894 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_13 0x481898 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_14 0x48189C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_BASE_HIGH_AR_15 0x4818A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_0 0x4818A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_1 0x4818A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_2 0x4818AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_3 0x4818B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_4 0x4818B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_5 0x4818B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_6 0x4818BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_7 0x4818C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_8 0x4818C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_9 0x4818C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_10 0x4818CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_11 0x4818D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_12 0x4818D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_13 0x4818D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_14 0x4818DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_LOW_AR_15 0x4818E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_0 0x4818E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_1 0x4818E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_2 0x4818EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_3 0x4818F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_4 0x4818F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_5 0x4818F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_6 0x4818FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_7 0x481900 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_8 0x481904 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_9 0x481908 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_10 0x48190C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_11 0x481910 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_12 0x481914 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_13 0x481918 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_14 0x48191C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_MASK_HIGH_AR_15 0x481920 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_0 0x481924 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_1 0x481928 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_2 0x48192C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_3 0x481930 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_4 0x481934 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_5 0x481938 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_6 0x48193C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_7 0x481940 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_8 0x481944 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_9 0x481948 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_10 0x48194C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_11 0x481950 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_12 0x481954 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_13 0x481958 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_14 0x48195C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_LOW_AR_15 0x481960 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_0 0x481964 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_1 0x481968 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_2 0x48196C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_3 0x481970 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_4 0x481974 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_5 0x481978 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_6 0x48197C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_7 0x481980 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_8 0x481984 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_9 0x481988 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_10 0x48198C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_11 0x481990 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_12 0x481994 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_13 0x481998 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_14 0x48199C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_BASE_HIGH_AR_15 0x4819A0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_0 0x4819A4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_1 0x4819A8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_2 0x4819AC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_3 0x4819B0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_4 0x4819B4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_5 0x4819B8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_6 0x4819BC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_7 0x4819C0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_8 0x4819C4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_9 0x4819C8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_10 0x4819CC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_11 0x4819D0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_12 0x4819D4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_13 0x4819D8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_14 0x4819DC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_LOW_AR_15 0x4819E0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_0 0x4819E4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_1 0x4819E8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_2 0x4819EC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_3 0x4819F0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_4 0x4819F4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_5 0x4819F8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_6 0x4819FC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_7 0x481A00 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_8 0x481A04 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_9 0x481A08 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_10 0x481A0C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_11 0x481A10 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_12 0x481A14 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_13 0x481A18 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_14 0x481A1C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_MASK_HIGH_AR_15 0x481A20 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AW 0x481A64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_SEC_HIT_AR 0x481A68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AW 0x481A6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RANGE_PRIV_HIT_AR 0x481A70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_CFG 0x481B64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_SHIFT 0x481B68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_0 0x481B6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_1 0x481B70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_2 0x481B74 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_3 0x481B78 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_4 0x481B7C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_5 0x481B80 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_6 0x481B84 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_EXPECTED_LAT_7 0x481B88 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_0 0x481BAC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_1 0x481BB0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_2 0x481BB4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_3 0x481BB8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_4 0x481BBC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_5 0x481BC0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_6 0x481BC4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_TOKEN_7 0x481BC8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_0 0x481BEC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_1 0x481BF0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_2 0x481BF4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_3 0x481BF8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_4 0x481BFC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_5 0x481C00 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_6 0x481C04 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_BANK_ID_7 0x481C08 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_RGL_WDT 0x481C2C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_WRAP 0x481C30 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_WRAP 0x481C34 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_WRAP 0x481C38 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_WRAP 0x481C3C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_WRAP 0x481C40 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_WRAP 0x481C44 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_WRAP 0x481C48 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_WRAP 0x481C4C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH0_CTR_CNT 0x481C50 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM0_CH1_CTR_CNT 0x481C54 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH0_CTR_CNT 0x481C58 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM1_CH1_CTR_CNT 0x481C5C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH0_CTR_CNT 0x481C60 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM2_CH1_CTR_CNT 0x481C64 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH0_CTR_CNT 0x481C68 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AR_HBM3_CH1_CTR_CNT 0x481C6C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_WRAP 0x481C70 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_WRAP 0x481C74 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_WRAP 0x481C78 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_WRAP 0x481C7C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_WRAP 0x481C80 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_WRAP 0x481C84 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_WRAP 0x481C88 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_WRAP 0x481C8C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH0_CTR_CNT 0x481C90 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM0_CH1_CTR_CNT 0x481C94 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH0_CTR_CNT 0x481C98 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM1_CH1_CTR_CNT 0x481C9C |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH0_CTR_CNT 0x481CA0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM2_CH1_CTR_CNT 0x481CA4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH0_CTR_CNT 0x481CA8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_E2E_AW_HBM3_CH1_CTR_CNT 0x481CAC |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_0 0x481CB0 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_1 0x481CB4 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_2 0x481CB8 |
| |
| #define mmDMA_IF_W_S_DOWN_CH0_NL_HBM_PC_SEL_3 0x481CBC |
| |
| #endif /* ASIC_REG_DMA_IF_W_S_DOWN_CH0_REGS_H_ */ |
