| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_NIC3_QM0_REGS_H_ |
| #define ASIC_REG_NIC3_QM0_REGS_H_ |
| |
| /* |
| ***************************************** |
| * NIC3_QM0 (Prototype: QMAN) |
| ***************************************** |
| */ |
| |
| #define mmNIC3_QM0_GLBL_CFG0 0xDA0000 |
| |
| #define mmNIC3_QM0_GLBL_CFG1 0xDA0004 |
| |
| #define mmNIC3_QM0_GLBL_PROT 0xDA0008 |
| |
| #define mmNIC3_QM0_GLBL_ERR_CFG 0xDA000C |
| |
| #define mmNIC3_QM0_GLBL_SECURE_PROPS_0 0xDA0010 |
| |
| #define mmNIC3_QM0_GLBL_SECURE_PROPS_1 0xDA0014 |
| |
| #define mmNIC3_QM0_GLBL_SECURE_PROPS_2 0xDA0018 |
| |
| #define mmNIC3_QM0_GLBL_SECURE_PROPS_3 0xDA001C |
| |
| #define mmNIC3_QM0_GLBL_SECURE_PROPS_4 0xDA0020 |
| |
| #define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_0 0xDA0024 |
| |
| #define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_1 0xDA0028 |
| |
| #define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_2 0xDA002C |
| |
| #define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_3 0xDA0030 |
| |
| #define mmNIC3_QM0_GLBL_NON_SECURE_PROPS_4 0xDA0034 |
| |
| #define mmNIC3_QM0_GLBL_STS0 0xDA0038 |
| |
| #define mmNIC3_QM0_GLBL_STS1_0 0xDA0040 |
| |
| #define mmNIC3_QM0_GLBL_STS1_1 0xDA0044 |
| |
| #define mmNIC3_QM0_GLBL_STS1_2 0xDA0048 |
| |
| #define mmNIC3_QM0_GLBL_STS1_3 0xDA004C |
| |
| #define mmNIC3_QM0_GLBL_STS1_4 0xDA0050 |
| |
| #define mmNIC3_QM0_GLBL_MSG_EN_0 0xDA0054 |
| |
| #define mmNIC3_QM0_GLBL_MSG_EN_1 0xDA0058 |
| |
| #define mmNIC3_QM0_GLBL_MSG_EN_2 0xDA005C |
| |
| #define mmNIC3_QM0_GLBL_MSG_EN_3 0xDA0060 |
| |
| #define mmNIC3_QM0_GLBL_MSG_EN_4 0xDA0068 |
| |
| #define mmNIC3_QM0_PQ_BASE_LO_0 0xDA0070 |
| |
| #define mmNIC3_QM0_PQ_BASE_LO_1 0xDA0074 |
| |
| #define mmNIC3_QM0_PQ_BASE_LO_2 0xDA0078 |
| |
| #define mmNIC3_QM0_PQ_BASE_LO_3 0xDA007C |
| |
| #define mmNIC3_QM0_PQ_BASE_HI_0 0xDA0080 |
| |
| #define mmNIC3_QM0_PQ_BASE_HI_1 0xDA0084 |
| |
| #define mmNIC3_QM0_PQ_BASE_HI_2 0xDA0088 |
| |
| #define mmNIC3_QM0_PQ_BASE_HI_3 0xDA008C |
| |
| #define mmNIC3_QM0_PQ_SIZE_0 0xDA0090 |
| |
| #define mmNIC3_QM0_PQ_SIZE_1 0xDA0094 |
| |
| #define mmNIC3_QM0_PQ_SIZE_2 0xDA0098 |
| |
| #define mmNIC3_QM0_PQ_SIZE_3 0xDA009C |
| |
| #define mmNIC3_QM0_PQ_PI_0 0xDA00A0 |
| |
| #define mmNIC3_QM0_PQ_PI_1 0xDA00A4 |
| |
| #define mmNIC3_QM0_PQ_PI_2 0xDA00A8 |
| |
| #define mmNIC3_QM0_PQ_PI_3 0xDA00AC |
| |
| #define mmNIC3_QM0_PQ_CI_0 0xDA00B0 |
| |
| #define mmNIC3_QM0_PQ_CI_1 0xDA00B4 |
| |
| #define mmNIC3_QM0_PQ_CI_2 0xDA00B8 |
| |
| #define mmNIC3_QM0_PQ_CI_3 0xDA00BC |
| |
| #define mmNIC3_QM0_PQ_CFG0_0 0xDA00C0 |
| |
| #define mmNIC3_QM0_PQ_CFG0_1 0xDA00C4 |
| |
| #define mmNIC3_QM0_PQ_CFG0_2 0xDA00C8 |
| |
| #define mmNIC3_QM0_PQ_CFG0_3 0xDA00CC |
| |
| #define mmNIC3_QM0_PQ_CFG1_0 0xDA00D0 |
| |
| #define mmNIC3_QM0_PQ_CFG1_1 0xDA00D4 |
| |
| #define mmNIC3_QM0_PQ_CFG1_2 0xDA00D8 |
| |
| #define mmNIC3_QM0_PQ_CFG1_3 0xDA00DC |
| |
| #define mmNIC3_QM0_PQ_ARUSER_31_11_0 0xDA00E0 |
| |
| #define mmNIC3_QM0_PQ_ARUSER_31_11_1 0xDA00E4 |
| |
| #define mmNIC3_QM0_PQ_ARUSER_31_11_2 0xDA00E8 |
| |
| #define mmNIC3_QM0_PQ_ARUSER_31_11_3 0xDA00EC |
| |
| #define mmNIC3_QM0_PQ_STS0_0 0xDA00F0 |
| |
| #define mmNIC3_QM0_PQ_STS0_1 0xDA00F4 |
| |
| #define mmNIC3_QM0_PQ_STS0_2 0xDA00F8 |
| |
| #define mmNIC3_QM0_PQ_STS0_3 0xDA00FC |
| |
| #define mmNIC3_QM0_PQ_STS1_0 0xDA0100 |
| |
| #define mmNIC3_QM0_PQ_STS1_1 0xDA0104 |
| |
| #define mmNIC3_QM0_PQ_STS1_2 0xDA0108 |
| |
| #define mmNIC3_QM0_PQ_STS1_3 0xDA010C |
| |
| #define mmNIC3_QM0_CQ_CFG0_0 0xDA0110 |
| |
| #define mmNIC3_QM0_CQ_CFG0_1 0xDA0114 |
| |
| #define mmNIC3_QM0_CQ_CFG0_2 0xDA0118 |
| |
| #define mmNIC3_QM0_CQ_CFG0_3 0xDA011C |
| |
| #define mmNIC3_QM0_CQ_CFG0_4 0xDA0120 |
| |
| #define mmNIC3_QM0_CQ_CFG1_0 0xDA0124 |
| |
| #define mmNIC3_QM0_CQ_CFG1_1 0xDA0128 |
| |
| #define mmNIC3_QM0_CQ_CFG1_2 0xDA012C |
| |
| #define mmNIC3_QM0_CQ_CFG1_3 0xDA0130 |
| |
| #define mmNIC3_QM0_CQ_CFG1_4 0xDA0134 |
| |
| #define mmNIC3_QM0_CQ_ARUSER_31_11_0 0xDA0138 |
| |
| #define mmNIC3_QM0_CQ_ARUSER_31_11_1 0xDA013C |
| |
| #define mmNIC3_QM0_CQ_ARUSER_31_11_2 0xDA0140 |
| |
| #define mmNIC3_QM0_CQ_ARUSER_31_11_3 0xDA0144 |
| |
| #define mmNIC3_QM0_CQ_ARUSER_31_11_4 0xDA0148 |
| |
| #define mmNIC3_QM0_CQ_STS0_0 0xDA014C |
| |
| #define mmNIC3_QM0_CQ_STS0_1 0xDA0150 |
| |
| #define mmNIC3_QM0_CQ_STS0_2 0xDA0154 |
| |
| #define mmNIC3_QM0_CQ_STS0_3 0xDA0158 |
| |
| #define mmNIC3_QM0_CQ_STS0_4 0xDA015C |
| |
| #define mmNIC3_QM0_CQ_STS1_0 0xDA0160 |
| |
| #define mmNIC3_QM0_CQ_STS1_1 0xDA0164 |
| |
| #define mmNIC3_QM0_CQ_STS1_2 0xDA0168 |
| |
| #define mmNIC3_QM0_CQ_STS1_3 0xDA016C |
| |
| #define mmNIC3_QM0_CQ_STS1_4 0xDA0170 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_0 0xDA0174 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_0 0xDA0178 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_0 0xDA017C |
| |
| #define mmNIC3_QM0_CQ_CTL_0 0xDA0180 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_1 0xDA0184 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_1 0xDA0188 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_1 0xDA018C |
| |
| #define mmNIC3_QM0_CQ_CTL_1 0xDA0190 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_2 0xDA0194 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_2 0xDA0198 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_2 0xDA019C |
| |
| #define mmNIC3_QM0_CQ_CTL_2 0xDA01A0 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_3 0xDA01A4 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_3 0xDA01A8 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_3 0xDA01AC |
| |
| #define mmNIC3_QM0_CQ_CTL_3 0xDA01B0 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_4 0xDA01B4 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_4 0xDA01B8 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_4 0xDA01BC |
| |
| #define mmNIC3_QM0_CQ_CTL_4 0xDA01C0 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_STS_0 0xDA01C4 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_STS_1 0xDA01C8 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_STS_2 0xDA01CC |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_STS_3 0xDA01D0 |
| |
| #define mmNIC3_QM0_CQ_PTR_LO_STS_4 0xDA01D4 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_STS_0 0xDA01D8 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_STS_1 0xDA01DC |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_STS_2 0xDA01E0 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_STS_3 0xDA01E4 |
| |
| #define mmNIC3_QM0_CQ_PTR_HI_STS_4 0xDA01E8 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_STS_0 0xDA01EC |
| |
| #define mmNIC3_QM0_CQ_TSIZE_STS_1 0xDA01F0 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_STS_2 0xDA01F4 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_STS_3 0xDA01F8 |
| |
| #define mmNIC3_QM0_CQ_TSIZE_STS_4 0xDA01FC |
| |
| #define mmNIC3_QM0_CQ_CTL_STS_0 0xDA0200 |
| |
| #define mmNIC3_QM0_CQ_CTL_STS_1 0xDA0204 |
| |
| #define mmNIC3_QM0_CQ_CTL_STS_2 0xDA0208 |
| |
| #define mmNIC3_QM0_CQ_CTL_STS_3 0xDA020C |
| |
| #define mmNIC3_QM0_CQ_CTL_STS_4 0xDA0210 |
| |
| #define mmNIC3_QM0_CQ_IFIFO_CNT_0 0xDA0214 |
| |
| #define mmNIC3_QM0_CQ_IFIFO_CNT_1 0xDA0218 |
| |
| #define mmNIC3_QM0_CQ_IFIFO_CNT_2 0xDA021C |
| |
| #define mmNIC3_QM0_CQ_IFIFO_CNT_3 0xDA0220 |
| |
| #define mmNIC3_QM0_CQ_IFIFO_CNT_4 0xDA0224 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_0 0xDA0228 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_1 0xDA022C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_2 0xDA0230 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_3 0xDA0234 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_LO_4 0xDA0238 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_0 0xDA023C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_1 0xDA0240 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_2 0xDA0244 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_3 0xDA0248 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE0_ADDR_HI_4 0xDA024C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_0 0xDA0250 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_1 0xDA0254 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_2 0xDA0258 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_3 0xDA025C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_LO_4 0xDA0260 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_0 0xDA0264 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_1 0xDA0268 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_2 0xDA026C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_3 0xDA0270 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE1_ADDR_HI_4 0xDA0274 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_0 0xDA0278 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_1 0xDA027C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_2 0xDA0280 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_3 0xDA0284 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_LO_4 0xDA0288 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_0 0xDA028C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_1 0xDA0290 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_2 0xDA0294 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_3 0xDA0298 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE2_ADDR_HI_4 0xDA029C |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_0 0xDA02A0 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_1 0xDA02A4 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_2 0xDA02A8 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_3 0xDA02AC |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_LO_4 0xDA02B0 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_0 0xDA02B4 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_1 0xDA02B8 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_2 0xDA02BC |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_3 0xDA02C0 |
| |
| #define mmNIC3_QM0_CP_MSG_BASE3_ADDR_HI_4 0xDA02C4 |
| |
| #define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_0 0xDA02C8 |
| |
| #define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_1 0xDA02CC |
| |
| #define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_2 0xDA02D0 |
| |
| #define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_3 0xDA02D4 |
| |
| #define mmNIC3_QM0_CP_LDMA_TSIZE_OFFSET_4 0xDA02D8 |
| |
| #define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xDA02E0 |
| |
| #define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xDA02E4 |
| |
| #define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xDA02E8 |
| |
| #define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xDA02EC |
| |
| #define mmNIC3_QM0_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xDA02F0 |
| |
| #define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_0 0xDA02F4 |
| |
| #define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_1 0xDA02F8 |
| |
| #define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_2 0xDA02FC |
| |
| #define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_3 0xDA0300 |
| |
| #define mmNIC3_QM0_CP_LDMA_DST_BASE_LO_OFFSET_4 0xDA0304 |
| |
| #define mmNIC3_QM0_CP_FENCE0_RDATA_0 0xDA0308 |
| |
| #define mmNIC3_QM0_CP_FENCE0_RDATA_1 0xDA030C |
| |
| #define mmNIC3_QM0_CP_FENCE0_RDATA_2 0xDA0310 |
| |
| #define mmNIC3_QM0_CP_FENCE0_RDATA_3 0xDA0314 |
| |
| #define mmNIC3_QM0_CP_FENCE0_RDATA_4 0xDA0318 |
| |
| #define mmNIC3_QM0_CP_FENCE1_RDATA_0 0xDA031C |
| |
| #define mmNIC3_QM0_CP_FENCE1_RDATA_1 0xDA0320 |
| |
| #define mmNIC3_QM0_CP_FENCE1_RDATA_2 0xDA0324 |
| |
| #define mmNIC3_QM0_CP_FENCE1_RDATA_3 0xDA0328 |
| |
| #define mmNIC3_QM0_CP_FENCE1_RDATA_4 0xDA032C |
| |
| #define mmNIC3_QM0_CP_FENCE2_RDATA_0 0xDA0330 |
| |
| #define mmNIC3_QM0_CP_FENCE2_RDATA_1 0xDA0334 |
| |
| #define mmNIC3_QM0_CP_FENCE2_RDATA_2 0xDA0338 |
| |
| #define mmNIC3_QM0_CP_FENCE2_RDATA_3 0xDA033C |
| |
| #define mmNIC3_QM0_CP_FENCE2_RDATA_4 0xDA0340 |
| |
| #define mmNIC3_QM0_CP_FENCE3_RDATA_0 0xDA0344 |
| |
| #define mmNIC3_QM0_CP_FENCE3_RDATA_1 0xDA0348 |
| |
| #define mmNIC3_QM0_CP_FENCE3_RDATA_2 0xDA034C |
| |
| #define mmNIC3_QM0_CP_FENCE3_RDATA_3 0xDA0350 |
| |
| #define mmNIC3_QM0_CP_FENCE3_RDATA_4 0xDA0354 |
| |
| #define mmNIC3_QM0_CP_FENCE0_CNT_0 0xDA0358 |
| |
| #define mmNIC3_QM0_CP_FENCE0_CNT_1 0xDA035C |
| |
| #define mmNIC3_QM0_CP_FENCE0_CNT_2 0xDA0360 |
| |
| #define mmNIC3_QM0_CP_FENCE0_CNT_3 0xDA0364 |
| |
| #define mmNIC3_QM0_CP_FENCE0_CNT_4 0xDA0368 |
| |
| #define mmNIC3_QM0_CP_FENCE1_CNT_0 0xDA036C |
| |
| #define mmNIC3_QM0_CP_FENCE1_CNT_1 0xDA0370 |
| |
| #define mmNIC3_QM0_CP_FENCE1_CNT_2 0xDA0374 |
| |
| #define mmNIC3_QM0_CP_FENCE1_CNT_3 0xDA0378 |
| |
| #define mmNIC3_QM0_CP_FENCE1_CNT_4 0xDA037C |
| |
| #define mmNIC3_QM0_CP_FENCE2_CNT_0 0xDA0380 |
| |
| #define mmNIC3_QM0_CP_FENCE2_CNT_1 0xDA0384 |
| |
| #define mmNIC3_QM0_CP_FENCE2_CNT_2 0xDA0388 |
| |
| #define mmNIC3_QM0_CP_FENCE2_CNT_3 0xDA038C |
| |
| #define mmNIC3_QM0_CP_FENCE2_CNT_4 0xDA0390 |
| |
| #define mmNIC3_QM0_CP_FENCE3_CNT_0 0xDA0394 |
| |
| #define mmNIC3_QM0_CP_FENCE3_CNT_1 0xDA0398 |
| |
| #define mmNIC3_QM0_CP_FENCE3_CNT_2 0xDA039C |
| |
| #define mmNIC3_QM0_CP_FENCE3_CNT_3 0xDA03A0 |
| |
| #define mmNIC3_QM0_CP_FENCE3_CNT_4 0xDA03A4 |
| |
| #define mmNIC3_QM0_CP_STS_0 0xDA03A8 |
| |
| #define mmNIC3_QM0_CP_STS_1 0xDA03AC |
| |
| #define mmNIC3_QM0_CP_STS_2 0xDA03B0 |
| |
| #define mmNIC3_QM0_CP_STS_3 0xDA03B4 |
| |
| #define mmNIC3_QM0_CP_STS_4 0xDA03B8 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_LO_0 0xDA03BC |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_LO_1 0xDA03C0 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_LO_2 0xDA03C4 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_LO_3 0xDA03C8 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_LO_4 0xDA03CC |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_HI_0 0xDA03D0 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_HI_1 0xDA03D4 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_HI_2 0xDA03D8 |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_HI_3 0xDA03DC |
| |
| #define mmNIC3_QM0_CP_CURRENT_INST_HI_4 0xDA03E0 |
| |
| #define mmNIC3_QM0_CP_BARRIER_CFG_0 0xDA03F4 |
| |
| #define mmNIC3_QM0_CP_BARRIER_CFG_1 0xDA03F8 |
| |
| #define mmNIC3_QM0_CP_BARRIER_CFG_2 0xDA03FC |
| |
| #define mmNIC3_QM0_CP_BARRIER_CFG_3 0xDA0400 |
| |
| #define mmNIC3_QM0_CP_BARRIER_CFG_4 0xDA0404 |
| |
| #define mmNIC3_QM0_CP_DBG_0_0 0xDA0408 |
| |
| #define mmNIC3_QM0_CP_DBG_0_1 0xDA040C |
| |
| #define mmNIC3_QM0_CP_DBG_0_2 0xDA0410 |
| |
| #define mmNIC3_QM0_CP_DBG_0_3 0xDA0414 |
| |
| #define mmNIC3_QM0_CP_DBG_0_4 0xDA0418 |
| |
| #define mmNIC3_QM0_CP_ARUSER_31_11_0 0xDA041C |
| |
| #define mmNIC3_QM0_CP_ARUSER_31_11_1 0xDA0420 |
| |
| #define mmNIC3_QM0_CP_ARUSER_31_11_2 0xDA0424 |
| |
| #define mmNIC3_QM0_CP_ARUSER_31_11_3 0xDA0428 |
| |
| #define mmNIC3_QM0_CP_ARUSER_31_11_4 0xDA042C |
| |
| #define mmNIC3_QM0_CP_AWUSER_31_11_0 0xDA0430 |
| |
| #define mmNIC3_QM0_CP_AWUSER_31_11_1 0xDA0434 |
| |
| #define mmNIC3_QM0_CP_AWUSER_31_11_2 0xDA0438 |
| |
| #define mmNIC3_QM0_CP_AWUSER_31_11_3 0xDA043C |
| |
| #define mmNIC3_QM0_CP_AWUSER_31_11_4 0xDA0440 |
| |
| #define mmNIC3_QM0_ARB_CFG_0 0xDA0A00 |
| |
| #define mmNIC3_QM0_ARB_CHOISE_Q_PUSH 0xDA0A04 |
| |
| #define mmNIC3_QM0_ARB_WRR_WEIGHT_0 0xDA0A08 |
| |
| #define mmNIC3_QM0_ARB_WRR_WEIGHT_1 0xDA0A0C |
| |
| #define mmNIC3_QM0_ARB_WRR_WEIGHT_2 0xDA0A10 |
| |
| #define mmNIC3_QM0_ARB_WRR_WEIGHT_3 0xDA0A14 |
| |
| #define mmNIC3_QM0_ARB_CFG_1 0xDA0A18 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_0 0xDA0A20 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_1 0xDA0A24 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_2 0xDA0A28 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_3 0xDA0A2C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_4 0xDA0A30 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_5 0xDA0A34 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_6 0xDA0A38 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_7 0xDA0A3C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_8 0xDA0A40 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_9 0xDA0A44 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_10 0xDA0A48 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_11 0xDA0A4C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_12 0xDA0A50 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_13 0xDA0A54 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_14 0xDA0A58 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_15 0xDA0A5C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_16 0xDA0A60 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_17 0xDA0A64 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_18 0xDA0A68 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_19 0xDA0A6C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_20 0xDA0A70 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_21 0xDA0A74 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_22 0xDA0A78 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_23 0xDA0A7C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_24 0xDA0A80 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_25 0xDA0A84 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_26 0xDA0A88 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_27 0xDA0A8C |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_28 0xDA0A90 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_29 0xDA0A94 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_30 0xDA0A98 |
| |
| #define mmNIC3_QM0_ARB_MST_AVAIL_CRED_31 0xDA0A9C |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_INC 0xDA0AA0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_0 0xDA0AA4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_1 0xDA0AA8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_2 0xDA0AAC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_3 0xDA0AB0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_4 0xDA0AB4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_5 0xDA0AB8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_6 0xDA0ABC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_7 0xDA0AC0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_8 0xDA0AC4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_9 0xDA0AC8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_10 0xDA0ACC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_11 0xDA0AD0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_12 0xDA0AD4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_13 0xDA0AD8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_14 0xDA0ADC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_15 0xDA0AE0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_16 0xDA0AE4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_17 0xDA0AE8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_18 0xDA0AEC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_19 0xDA0AF0 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_20 0xDA0AF4 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_21 0xDA0AF8 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_22 0xDA0AFC |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_23 0xDA0B00 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_24 0xDA0B04 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_25 0xDA0B08 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_26 0xDA0B0C |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_27 0xDA0B10 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_28 0xDA0B14 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_29 0xDA0B18 |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_30 0xDA0B1C |
| |
| #define mmNIC3_QM0_ARB_MST_CHOISE_PUSH_OFST_31 0xDA0B20 |
| |
| #define mmNIC3_QM0_ARB_SLV_MASTER_INC_CRED_OFST 0xDA0B28 |
| |
| #define mmNIC3_QM0_ARB_MST_SLAVE_EN 0xDA0B2C |
| |
| #define mmNIC3_QM0_ARB_MST_QUIET_PER 0xDA0B34 |
| |
| #define mmNIC3_QM0_ARB_SLV_CHOISE_WDT 0xDA0B38 |
| |
| #define mmNIC3_QM0_ARB_SLV_ID 0xDA0B3C |
| |
| #define mmNIC3_QM0_ARB_MSG_MAX_INFLIGHT 0xDA0B44 |
| |
| #define mmNIC3_QM0_ARB_MSG_AWUSER_31_11 0xDA0B48 |
| |
| #define mmNIC3_QM0_ARB_MSG_AWUSER_SEC_PROP 0xDA0B4C |
| |
| #define mmNIC3_QM0_ARB_MSG_AWUSER_NON_SEC_PROP 0xDA0B50 |
| |
| #define mmNIC3_QM0_ARB_BASE_LO 0xDA0B54 |
| |
| #define mmNIC3_QM0_ARB_BASE_HI 0xDA0B58 |
| |
| #define mmNIC3_QM0_ARB_STATE_STS 0xDA0B80 |
| |
| #define mmNIC3_QM0_ARB_CHOISE_FULLNESS_STS 0xDA0B84 |
| |
| #define mmNIC3_QM0_ARB_MSG_STS 0xDA0B88 |
| |
| #define mmNIC3_QM0_ARB_SLV_CHOISE_Q_HEAD 0xDA0B8C |
| |
| #define mmNIC3_QM0_ARB_ERR_CAUSE 0xDA0B9C |
| |
| #define mmNIC3_QM0_ARB_ERR_MSG_EN 0xDA0BA0 |
| |
| #define mmNIC3_QM0_ARB_ERR_STS_DRP 0xDA0BA8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_0 0xDA0BB0 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_1 0xDA0BB4 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_2 0xDA0BB8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_3 0xDA0BBC |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_4 0xDA0BC0 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_5 0xDA0BC4 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_6 0xDA0BC8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_7 0xDA0BCC |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_8 0xDA0BD0 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_9 0xDA0BD4 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_10 0xDA0BD8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_11 0xDA0BDC |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_12 0xDA0BE0 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_13 0xDA0BE4 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_14 0xDA0BE8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_15 0xDA0BEC |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_16 0xDA0BF0 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_17 0xDA0BF4 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_18 0xDA0BF8 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_19 0xDA0BFC |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_20 0xDA0C00 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_21 0xDA0C04 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_22 0xDA0C08 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_23 0xDA0C0C |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_24 0xDA0C10 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_25 0xDA0C14 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_26 0xDA0C18 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_27 0xDA0C1C |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_28 0xDA0C20 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_29 0xDA0C24 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_30 0xDA0C28 |
| |
| #define mmNIC3_QM0_ARB_MST_CRED_STS_31 0xDA0C2C |
| |
| #define mmNIC3_QM0_CGM_CFG 0xDA0C70 |
| |
| #define mmNIC3_QM0_CGM_STS 0xDA0C74 |
| |
| #define mmNIC3_QM0_CGM_CFG1 0xDA0C78 |
| |
| #define mmNIC3_QM0_LOCAL_RANGE_BASE 0xDA0C80 |
| |
| #define mmNIC3_QM0_LOCAL_RANGE_SIZE 0xDA0C84 |
| |
| #define mmNIC3_QM0_CSMR_STRICT_PRIO_CFG 0xDA0C90 |
| |
| #define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_1 0xDA0C94 |
| |
| #define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_0 0xDA0C98 |
| |
| #define mmNIC3_QM0_LBW_WR_RATE_LIM_CFG_1 0xDA0C9C |
| |
| #define mmNIC3_QM0_HBW_RD_RATE_LIM_CFG_0 0xDA0CA0 |
| |
| #define mmNIC3_QM0_GLBL_AXCACHE 0xDA0CA4 |
| |
| #define mmNIC3_QM0_IND_GW_APB_CFG 0xDA0CB0 |
| |
| #define mmNIC3_QM0_IND_GW_APB_WDATA 0xDA0CB4 |
| |
| #define mmNIC3_QM0_IND_GW_APB_RDATA 0xDA0CB8 |
| |
| #define mmNIC3_QM0_IND_GW_APB_STATUS 0xDA0CBC |
| |
| #define mmNIC3_QM0_GLBL_ERR_ADDR_LO 0xDA0CD0 |
| |
| #define mmNIC3_QM0_GLBL_ERR_ADDR_HI 0xDA0CD4 |
| |
| #define mmNIC3_QM0_GLBL_ERR_WDATA 0xDA0CD8 |
| |
| #define mmNIC3_QM0_GLBL_MEM_INIT_BUSY 0xDA0D00 |
| |
| #endif /* ASIC_REG_NIC3_QM0_REGS_H_ */ |
