| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ |
| #define ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ |
| |
| /* |
| ***************************************** |
| * SIF_RTR_CTRL_0 (Prototype: RTR_CTRL) |
| ***************************************** |
| */ |
| |
| #define mmSIF_RTR_CTRL_0_PERM_SEL 0x306108 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_0 0x306114 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_1 0x306118 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_2 0x30611C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_3 0x306120 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_4 0x306124 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_5 0x306128 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_6 0x30612C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_7 0x306130 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_8 0x306134 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_9 0x306138 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_10 0x30613C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_11 0x306140 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_12 0x306144 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_13 0x306148 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_14 0x30614C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_15 0x306150 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_16 0x306154 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_17 0x306158 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_18 0x30615C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_19 0x306160 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_20 0x306164 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_21 0x306168 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_22 0x30616C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_23 0x306170 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_24 0x306174 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_25 0x306178 |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_26 0x30617C |
| |
| #define mmSIF_RTR_CTRL_0_HBM_POLY_H3_27 0x306180 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_0 0x306184 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_1 0x306188 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_2 0x30618C |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_3 0x306190 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_4 0x306194 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_5 0x306198 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_6 0x30619C |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_7 0x3061A0 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_8 0x3061A4 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_9 0x3061A8 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_10 0x3061AC |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_11 0x3061B0 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_12 0x3061B4 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_13 0x3061B8 |
| |
| #define mmSIF_RTR_CTRL_0_SRAM_POLY_H3_14 0x3061BC |
| |
| #define mmSIF_RTR_CTRL_0_SCRAM_SRAM_EN 0x30626C |
| |
| #define mmSIF_RTR_CTRL_0_RL_HBM_EN 0x306274 |
| |
| #define mmSIF_RTR_CTRL_0_RL_HBM_SAT 0x306278 |
| |
| #define mmSIF_RTR_CTRL_0_RL_HBM_RST 0x30627C |
| |
| #define mmSIF_RTR_CTRL_0_RL_HBM_TIMEOUT 0x306280 |
| |
| #define mmSIF_RTR_CTRL_0_SCRAM_HBM_EN 0x306284 |
| |
| #define mmSIF_RTR_CTRL_0_RL_PCI_EN 0x306288 |
| |
| #define mmSIF_RTR_CTRL_0_RL_PCI_SAT 0x30628C |
| |
| #define mmSIF_RTR_CTRL_0_RL_PCI_RST 0x306290 |
| |
| #define mmSIF_RTR_CTRL_0_RL_PCI_TIMEOUT 0x306294 |
| |
| #define mmSIF_RTR_CTRL_0_RL_SRAM_EN 0x30629C |
| |
| #define mmSIF_RTR_CTRL_0_RL_SRAM_SAT 0x3062A0 |
| |
| #define mmSIF_RTR_CTRL_0_RL_SRAM_RST 0x3062A4 |
| |
| #define mmSIF_RTR_CTRL_0_RL_SRAM_TIMEOUT 0x3062AC |
| |
| #define mmSIF_RTR_CTRL_0_RL_SRAM_RED 0x3062B4 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_HBM_EN 0x3062EC |
| |
| #define mmSIF_RTR_CTRL_0_E2E_PCI_EN 0x3062F0 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_HBM_WR_SIZE 0x3062F4 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_PCI_WR_SIZE 0x3062F8 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET_EN 0x306404 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_SET 0x306408 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_WRAP 0x30640C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_PCI_CTR_CNT 0x306410 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET_EN 0x306414 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM_CTR_SET 0x306418 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_HBM_RD_SIZE 0x30641C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_PCI_RD_SIZE 0x306420 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET_EN 0x306424 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_SET 0x306428 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_WRAP 0x30642C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_PCI_CTR_CNT 0x306430 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET_EN 0x306434 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM_CTR_SET 0x306438 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_SEL_0 0x306450 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_SEL_1 0x306454 |
| |
| #define mmSIF_RTR_CTRL_0_NON_LIN_EN 0x306480 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_0 0x306500 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_1 0x306504 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_2 0x306508 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_3 0x30650C |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_BANK_4 0x306510 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_0 0x306514 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_1 0x306520 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_2 0x306524 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_3 0x306528 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_4 0x30652C |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_5 0x306530 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_6 0x306534 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_7 0x306538 |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_8 0x30653C |
| |
| #define mmSIF_RTR_CTRL_0_NL_SRAM_OFFSET_9 0x306540 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_0 0x306550 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_1 0x306554 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_2 0x306558 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_3 0x30655C |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_4 0x306560 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_5 0x306564 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_6 0x306568 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_7 0x30656C |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_8 0x306570 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_9 0x306574 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_10 0x306578 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_11 0x30657C |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_12 0x306580 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_13 0x306584 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_14 0x306588 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_15 0x30658C |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_16 0x306590 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_17 0x306594 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_OFFSET_18 0x306598 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_0 0x3065E4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_1 0x3065E8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_2 0x3065EC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_3 0x3065F0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_4 0x3065F4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_5 0x3065F8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_6 0x3065FC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_7 0x306600 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_8 0x306604 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_9 0x306608 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_10 0x30660C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_11 0x306610 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_12 0x306614 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_13 0x306618 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_14 0x30661C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AW_15 0x306620 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_0 0x306624 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_1 0x306628 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_2 0x30662C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_3 0x306630 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_4 0x306634 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_5 0x306638 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_6 0x30663C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_7 0x306640 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_8 0x306644 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_9 0x306648 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_10 0x30664C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_11 0x306650 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_12 0x306654 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_13 0x306658 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_14 0x30665C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AW_15 0x306660 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_0 0x306664 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_1 0x306668 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_2 0x30666C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_3 0x306670 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_4 0x306674 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_5 0x306678 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_6 0x30667C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_7 0x306680 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_8 0x306684 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_9 0x306688 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_10 0x30668C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_11 0x306690 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_12 0x306694 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_13 0x306698 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_14 0x30669C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AW_15 0x3066A0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_0 0x3066A4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_1 0x3066A8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_2 0x3066AC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_3 0x3066B0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_4 0x3066B4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_5 0x3066B8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_6 0x3066BC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_7 0x3066C0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_8 0x3066C4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_9 0x3066C8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_10 0x3066CC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_11 0x3066D0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_12 0x3066D4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_13 0x3066D8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_14 0x3066DC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AW_15 0x3066E0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_0 0x3066E4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_1 0x3066E8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_2 0x3066EC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_3 0x3066F0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_4 0x3066F4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_5 0x3066F8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_6 0x3066FC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_7 0x306700 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_8 0x306704 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_9 0x306708 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_10 0x30670C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_11 0x306710 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_12 0x306714 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_13 0x306718 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_14 0x30671C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AW_15 0x306720 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_0 0x306724 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_1 0x306728 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_2 0x30672C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_3 0x306730 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_4 0x306734 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_5 0x306738 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_6 0x30673C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_7 0x306740 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_8 0x306744 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_9 0x306748 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_10 0x30674C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_11 0x306750 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_12 0x306754 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_13 0x306758 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_14 0x30675C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AW_15 0x306760 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_0 0x306764 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_1 0x306768 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_2 0x30676C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_3 0x306770 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_4 0x306774 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_5 0x306778 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_6 0x30677C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_7 0x306780 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_8 0x306784 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_9 0x306788 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_10 0x30678C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_11 0x306790 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_12 0x306794 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_13 0x306798 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_14 0x30679C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AW_15 0x3067A0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_0 0x3067A4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_1 0x3067A8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_2 0x3067AC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_3 0x3067B0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_4 0x3067B4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_5 0x3067B8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_6 0x3067BC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_7 0x3067C0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_8 0x3067C4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_9 0x3067C8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_10 0x3067CC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_11 0x3067D0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_12 0x3067D4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_13 0x3067D8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_14 0x3067DC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AW_15 0x3067E0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_0 0x306824 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_1 0x306828 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_2 0x30682C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_3 0x306830 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_4 0x306834 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_5 0x306838 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_6 0x30683C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_7 0x306840 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_8 0x306844 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_9 0x306848 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_10 0x30684C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_11 0x306850 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_12 0x306854 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_13 0x306858 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_14 0x30685C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_LOW_AR_15 0x306860 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_0 0x306864 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_1 0x306868 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_2 0x30686C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_3 0x306870 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_4 0x306874 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_5 0x306878 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_6 0x30687C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_7 0x306880 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_8 0x306884 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_9 0x306888 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_10 0x30688C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_11 0x306890 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_12 0x306894 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_13 0x306898 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_14 0x30689C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_BASE_HIGH_AR_15 0x3068A0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_0 0x3068A4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_1 0x3068A8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_2 0x3068AC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_3 0x3068B0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_4 0x3068B4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_5 0x3068B8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_6 0x3068BC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_7 0x3068C0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_8 0x3068C4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_9 0x3068C8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_10 0x3068CC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_11 0x3068D0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_12 0x3068D4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_13 0x3068D8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_14 0x3068DC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_LOW_AR_15 0x3068E0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_0 0x3068E4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_1 0x3068E8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_2 0x3068EC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_3 0x3068F0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_4 0x3068F4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_5 0x3068F8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_6 0x3068FC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_7 0x306900 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_8 0x306904 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_9 0x306908 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_10 0x30690C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_11 0x306910 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_12 0x306914 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_13 0x306918 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_14 0x30691C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_MASK_HIGH_AR_15 0x306920 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_0 0x306924 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_1 0x306928 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_2 0x30692C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_3 0x306930 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_4 0x306934 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_5 0x306938 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_6 0x30693C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_7 0x306940 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_8 0x306944 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_9 0x306948 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_10 0x30694C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_11 0x306950 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_12 0x306954 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_13 0x306958 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_14 0x30695C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_LOW_AR_15 0x306960 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_0 0x306964 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_1 0x306968 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_2 0x30696C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_3 0x306970 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_4 0x306974 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_5 0x306978 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_6 0x30697C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_7 0x306980 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_8 0x306984 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_9 0x306988 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_10 0x30698C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_11 0x306990 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_12 0x306994 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_13 0x306998 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_14 0x30699C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_BASE_HIGH_AR_15 0x3069A0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_0 0x3069A4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_1 0x3069A8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_2 0x3069AC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_3 0x3069B0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_4 0x3069B4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_5 0x3069B8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_6 0x3069BC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_7 0x3069C0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_8 0x3069C4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_9 0x3069C8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_10 0x3069CC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_11 0x3069D0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_12 0x3069D4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_13 0x3069D8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_14 0x3069DC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_LOW_AR_15 0x3069E0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_0 0x3069E4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_1 0x3069E8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_2 0x3069EC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_3 0x3069F0 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_4 0x3069F4 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_5 0x3069F8 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_6 0x3069FC |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_7 0x306A00 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_8 0x306A04 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_9 0x306A08 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_10 0x306A0C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_11 0x306A10 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_12 0x306A14 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_13 0x306A18 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_14 0x306A1C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_MASK_HIGH_AR_15 0x306A20 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AW 0x306A64 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_SEC_HIT_AR 0x306A68 |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AW 0x306A6C |
| |
| #define mmSIF_RTR_CTRL_0_RANGE_PRIV_HIT_AR 0x306A70 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_CFG 0x306B64 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_SHIFT 0x306B68 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_0 0x306B6C |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_1 0x306B70 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_2 0x306B74 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_3 0x306B78 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_4 0x306B7C |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_5 0x306B80 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_6 0x306B84 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_EXPECTED_LAT_7 0x306B88 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_0 0x306BAC |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_1 0x306BB0 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_2 0x306BB4 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_3 0x306BB8 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_4 0x306BBC |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_5 0x306BC0 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_6 0x306BC4 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_TOKEN_7 0x306BC8 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_0 0x306BEC |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_1 0x306BF0 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_2 0x306BF4 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_3 0x306BF8 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_4 0x306BFC |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_5 0x306C00 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_6 0x306C04 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_BANK_ID_7 0x306C08 |
| |
| #define mmSIF_RTR_CTRL_0_RGL_WDT 0x306C2C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_WRAP 0x306C30 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_WRAP 0x306C34 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_WRAP 0x306C38 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_WRAP 0x306C3C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_WRAP 0x306C40 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_WRAP 0x306C44 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_WRAP 0x306C48 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_WRAP 0x306C4C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH0_CTR_CNT 0x306C50 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM0_CH1_CTR_CNT 0x306C54 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH0_CTR_CNT 0x306C58 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM1_CH1_CTR_CNT 0x306C5C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH0_CTR_CNT 0x306C60 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM2_CH1_CTR_CNT 0x306C64 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH0_CTR_CNT 0x306C68 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AR_HBM3_CH1_CTR_CNT 0x306C6C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_WRAP 0x306C70 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_WRAP 0x306C74 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_WRAP 0x306C78 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_WRAP 0x306C7C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_WRAP 0x306C80 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_WRAP 0x306C84 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_WRAP 0x306C88 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_WRAP 0x306C8C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH0_CTR_CNT 0x306C90 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM0_CH1_CTR_CNT 0x306C94 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH0_CTR_CNT 0x306C98 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM1_CH1_CTR_CNT 0x306C9C |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH0_CTR_CNT 0x306CA0 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM2_CH1_CTR_CNT 0x306CA4 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH0_CTR_CNT 0x306CA8 |
| |
| #define mmSIF_RTR_CTRL_0_E2E_AW_HBM3_CH1_CTR_CNT 0x306CAC |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_0 0x306CB0 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_1 0x306CB4 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_2 0x306CB8 |
| |
| #define mmSIF_RTR_CTRL_0_NL_HBM_PC_SEL_3 0x306CBC |
| |
| #endif /* ASIC_REG_SIF_RTR_CTRL_0_REGS_H_ */ |
