| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC3_CFG_REGS_H_ |
| #define ASIC_REG_TPC3_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC3_CFG (Prototype: TPC) |
| ***************************************** |
| */ |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778 |
| |
| #define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C |
| |
| #define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780 |
| |
| #define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784 |
| |
| #define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788 |
| |
| #define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C |
| |
| #define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790 |
| |
| #define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794 |
| |
| #define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798 |
| |
| #define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C |
| |
| #define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0 |
| |
| #define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4 |
| |
| #define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8 |
| |
| #define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC |
| |
| #define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0 |
| |
| #define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4 |
| |
| #define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8 |
| |
| #define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC |
| |
| #define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC |
| |
| #define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC |
| |
| #define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC |
| |
| #define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC |
| |
| #define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C |
| |
| #define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C |
| |
| #define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C |
| |
| #define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838 |
| |
| #define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C |
| |
| #define mmTPC3_CFG_ROUND_CSR 0xEC68FC |
| |
| #define mmTPC3_CFG_PROT 0xEC6900 |
| |
| #define mmTPC3_CFG_SEMAPHORE 0xEC6908 |
| |
| #define mmTPC3_CFG_VFLAGS 0xEC690C |
| |
| #define mmTPC3_CFG_SFLAGS 0xEC6910 |
| |
| #define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918 |
| |
| #define mmTPC3_CFG_STATUS 0xEC691C |
| |
| #define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920 |
| |
| #define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924 |
| |
| #define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C |
| |
| #define mmTPC3_CFG_TPC_CMD 0xEC6930 |
| |
| #define mmTPC3_CFG_TPC_EXECUTE 0xEC6938 |
| |
| #define mmTPC3_CFG_TPC_STALL 0xEC693C |
| |
| #define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940 |
| |
| #define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944 |
| |
| #define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948 |
| |
| #define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950 |
| |
| #define mmTPC3_CFG_MSS_CONFIG 0xEC6954 |
| |
| #define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958 |
| |
| #define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C |
| |
| #define mmTPC3_CFG_WQ_CREDITS 0xEC6960 |
| |
| #define mmTPC3_CFG_ARUSER_LO 0xEC6964 |
| |
| #define mmTPC3_CFG_ARUSER_HI 0xEC6968 |
| |
| #define mmTPC3_CFG_AWUSER_LO 0xEC696C |
| |
| #define mmTPC3_CFG_AWUSER_HI 0xEC6970 |
| |
| #define mmTPC3_CFG_OPCODE_EXEC 0xEC6974 |
| |
| #define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978 |
| |
| #define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C |
| |
| #define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980 |
| |
| #define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984 |
| |
| #define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988 |
| |
| #define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C |
| |
| #define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990 |
| |
| #define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994 |
| |
| #define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998 |
| |
| #define mmTPC3_CFG_TSB_CFG 0xEC699C |
| |
| #define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0 |
| |
| #define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4 |
| |
| #define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8 |
| |
| #define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC |
| |
| #define mmTPC3_CFG_DBGMEM_RC 0xEC69B0 |
| |
| #define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4 |
| |
| #define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8 |
| |
| #define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC |
| |
| #define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0 |
| |
| #define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8 |
| |
| #define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30 |
| |
| #define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68 |
| |
| #define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10 |
| |
| #define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48 |
| |
| #define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80 |
| |
| #define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28 |
| |
| #define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60 |
| |
| #define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98 |
| |
| #define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08 |
| |
| #define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40 |
| |
| #define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78 |
| |
| #define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C |
| |
| #define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80 |
| |
| #define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84 |
| |
| #define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88 |
| |
| #define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C |
| |
| #define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90 |
| |
| #define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94 |
| |
| #define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98 |
| |
| #define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C |
| |
| #define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0 |
| |
| #define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4 |
| |
| #define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8 |
| |
| #define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC |
| |
| #define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0 |
| |
| #define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4 |
| |
| #define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8 |
| |
| #define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC |
| |
| #define mmTPC3_CFG_QM_SRF_0 0xEC6DC0 |
| |
| #define mmTPC3_CFG_QM_SRF_1 0xEC6DC4 |
| |
| #define mmTPC3_CFG_QM_SRF_2 0xEC6DC8 |
| |
| #define mmTPC3_CFG_QM_SRF_3 0xEC6DCC |
| |
| #define mmTPC3_CFG_QM_SRF_4 0xEC6DD0 |
| |
| #define mmTPC3_CFG_QM_SRF_5 0xEC6DD4 |
| |
| #define mmTPC3_CFG_QM_SRF_6 0xEC6DD8 |
| |
| #define mmTPC3_CFG_QM_SRF_7 0xEC6DDC |
| |
| #define mmTPC3_CFG_QM_SRF_8 0xEC6DE0 |
| |
| #define mmTPC3_CFG_QM_SRF_9 0xEC6DE4 |
| |
| #define mmTPC3_CFG_QM_SRF_10 0xEC6DE8 |
| |
| #define mmTPC3_CFG_QM_SRF_11 0xEC6DEC |
| |
| #define mmTPC3_CFG_QM_SRF_12 0xEC6DF0 |
| |
| #define mmTPC3_CFG_QM_SRF_13 0xEC6DF4 |
| |
| #define mmTPC3_CFG_QM_SRF_14 0xEC6DF8 |
| |
| #define mmTPC3_CFG_QM_SRF_15 0xEC6DFC |
| |
| #define mmTPC3_CFG_QM_SRF_16 0xEC6E00 |
| |
| #define mmTPC3_CFG_QM_SRF_17 0xEC6E04 |
| |
| #define mmTPC3_CFG_QM_SRF_18 0xEC6E08 |
| |
| #define mmTPC3_CFG_QM_SRF_19 0xEC6E0C |
| |
| #define mmTPC3_CFG_QM_SRF_20 0xEC6E10 |
| |
| #define mmTPC3_CFG_QM_SRF_21 0xEC6E14 |
| |
| #define mmTPC3_CFG_QM_SRF_22 0xEC6E18 |
| |
| #define mmTPC3_CFG_QM_SRF_23 0xEC6E1C |
| |
| #define mmTPC3_CFG_QM_SRF_24 0xEC6E20 |
| |
| #define mmTPC3_CFG_QM_SRF_25 0xEC6E24 |
| |
| #define mmTPC3_CFG_QM_SRF_26 0xEC6E28 |
| |
| #define mmTPC3_CFG_QM_SRF_27 0xEC6E2C |
| |
| #define mmTPC3_CFG_QM_SRF_28 0xEC6E30 |
| |
| #define mmTPC3_CFG_QM_SRF_29 0xEC6E34 |
| |
| #define mmTPC3_CFG_QM_SRF_30 0xEC6E38 |
| |
| #define mmTPC3_CFG_QM_SRF_31 0xEC6E3C |
| |
| #endif /* ASIC_REG_TPC3_CFG_REGS_H_ */ |
