| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Device Tree Source for OMAP3 SoC |
| * |
| * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| #include <dt-bindings/bus/ti-sysc.h> |
| #include <dt-bindings/media/omap3-isp.h> |
| |
| #include "omap3.dtsi" |
| |
| / { |
| aliases { |
| serial3 = &uart4; |
| }; |
| |
| cpus { |
| /* OMAP3630/OMAP37xx variants OPP50 to OPP130 and OPP1G */ |
| cpu: cpu@0 { |
| operating-points-v2 = <&cpu0_opp_table>; |
| |
| vbb-supply = <&abb_mpu_iva>; |
| clock-latency = <300000>; /* From omap-cpufreq driver */ |
| #cooling-cells = <2>; |
| }; |
| }; |
| |
| cpu0_opp_table: opp-table { |
| compatible = "operating-points-v2-ti-cpu"; |
| syscon = <&scm_conf>; |
| |
| opp-50-300000000 { |
| /* OPP50 */ |
| opp-hz = /bits/ 64 <300000000>; |
| /* |
| * we currently only select the max voltage from table |
| * Table 4-19 of the DM3730 Data sheet (SPRS685B) |
| * Format is: cpu0-supply: <target min max> |
| * vbb-supply: <target min max> |
| */ |
| opp-microvolt = <1012500 1012500 1012500>, |
| <1012500 1012500 1012500>; |
| /* |
| * first value is silicon revision bit mask |
| * second one is "speed binned" bit mask |
| */ |
| opp-supported-hw = <0xffffffff 3>; |
| opp-suspend; |
| }; |
| |
| opp-100-600000000 { |
| /* OPP100 */ |
| opp-hz = /bits/ 64 <600000000>; |
| opp-microvolt = <1200000 1200000 1200000>, |
| <1200000 1200000 1200000>; |
| opp-supported-hw = <0xffffffff 3>; |
| }; |
| |
| opp-130-800000000 { |
| /* OPP130 */ |
| opp-hz = /bits/ 64 <800000000>; |
| opp-microvolt = <1325000 1325000 1325000>, |
| <1325000 1325000 1325000>; |
| opp-supported-hw = <0xffffffff 3>; |
| }; |
| |
| opp-1000000000 { |
| /* OPP1G */ |
| opp-hz = /bits/ 64 <1000000000>; |
| opp-microvolt = <1375000 1375000 1375000>, |
| <1375000 1375000 1375000>; |
| /* only on am/dm37x with speed-binned bit set */ |
| opp-supported-hw = <0xffffffff 2>; |
| }; |
| }; |
| |
| opp_supply_mpu_iva: opp-supply { |
| compatible = "ti,omap-opp-supply"; |
| ti,absolute-max-voltage-uv = <1375000>; |
| }; |
| |
| ocp@68000000 { |
| uart4: serial@49042000 { |
| compatible = "ti,omap3-uart"; |
| reg = <0x49042000 0x400>; |
| interrupts = <80>; |
| dmas = <&sdma 81 &sdma 82>; |
| dma-names = "tx", "rx"; |
| ti,hwmods = "uart4"; |
| clock-frequency = <48000000>; |
| }; |
| |
| abb_mpu_iva: regulator-abb-mpu { |
| compatible = "ti,abb-v1"; |
| regulator-name = "abb_mpu_iva"; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| reg = <0x483072f0 0x8>, <0x48306818 0x4>; |
| reg-names = "base-address", "int-address"; |
| ti,tranxdone-status-mask = <0x4000000>; |
| clocks = <&sys_ck>; |
| ti,settling-time = <30>; |
| ti,clock-cycles = <8>; |
| ti,abb_info = < |
| /*uV ABB efuse rbb_m fbb_m vset_m*/ |
| 1012500 0 0 0 0 0 |
| 1200000 0 0 0 0 0 |
| 1325000 0 0 0 0 0 |
| 1375000 1 0 0 0 0 |
| >; |
| }; |
| |
| omap3_pmx_core2: pinmux@480025a0 { |
| compatible = "ti,omap3-padconf", "pinctrl-single"; |
| reg = <0x480025a0 0x5c>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| #pinctrl-cells = <1>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| pinctrl-single,register-width = <16>; |
| pinctrl-single,function-mask = <0xff1f>; |
| }; |
| |
| isp: isp@480bc000 { |
| compatible = "ti,omap3-isp"; |
| reg = <0x480bc000 0x12fc |
| 0x480bd800 0x0600>; |
| interrupts = <24>; |
| iommus = <&mmu_isp>; |
| syscon = <&scm_conf 0x2f0>; |
| ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; |
| #clock-cells = <1>; |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| bandgap: bandgap@48002524 { |
| reg = <0x48002524 0x4>; |
| compatible = "ti,omap36xx-bandgap"; |
| #thermal-sensor-cells = <0>; |
| }; |
| |
| target-module@480cb000 { |
| compatible = "ti,sysc-omap3630-sr", "ti,sysc"; |
| ti,hwmods = "smartreflex_core"; |
| reg = <0x480cb038 0x4>; |
| reg-names = "sysc"; |
| ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| clocks = <&sr2_fck>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x480cb000 0x001000>; |
| |
| smartreflex_core: smartreflex@0 { |
| compatible = "ti,omap3-smartreflex-core"; |
| reg = <0 0x400>; |
| interrupts = <19>; |
| }; |
| }; |
| |
| target-module@480c9000 { |
| compatible = "ti,sysc-omap3630-sr", "ti,sysc"; |
| ti,hwmods = "smartreflex_mpu_iva"; |
| reg = <0x480c9038 0x4>; |
| reg-names = "sysc"; |
| ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| clocks = <&sr1_fck>; |
| clock-names = "fck"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x480c9000 0x001000>; |
| |
| |
| smartreflex_mpu_iva: smartreflex@480c9000 { |
| compatible = "ti,omap3-smartreflex-mpu-iva"; |
| reg = <0 0x400>; |
| interrupts = <18>; |
| }; |
| }; |
| |
| /* |
| * Note that the sysconfig register layout is a subset of the |
| * "ti,sysc-omap4" type register with just sidle and midle bits |
| * available while omap34xx has "ti,sysc-omap2" type sysconfig. |
| */ |
| sgx_module: target-module@50000000 { |
| compatible = "ti,sysc-omap4", "ti,sysc"; |
| reg = <0x5000fe00 0x4>, |
| <0x5000fe10 0x4>; |
| reg-names = "rev", "sysc"; |
| ti,sysc-midle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
| <SYSC_IDLE_NO>, |
| <SYSC_IDLE_SMART>; |
| clocks = <&sgx_fck>, <&sgx_ick>; |
| clock-names = "fck", "ick"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x50000000 0x2000000>; |
| |
| gpu@0 { |
| compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; |
| reg = <0x0 0x2000000>; /* 32MB */ |
| interrupts = <21>; |
| }; |
| }; |
| }; |
| |
| thermal_zones: thermal-zones { |
| #include "omap3-cpu-thermal.dtsi" |
| }; |
| }; |
| |
| &sdma { |
| compatible = "ti,omap3630-sdma", "ti,omap-sdma"; |
| }; |
| |
| /* OMAP3630 needs dss_96m_fck for VENC */ |
| &venc { |
| clocks = <&dss_tv_fck>, <&dss_96m_fck>; |
| clock-names = "fck", "tv_dac_clk"; |
| }; |
| |
| &ssi { |
| status = "okay"; |
| |
| clocks = <&ssi_ssr_fck>, |
| <&ssi_sst_fck>, |
| <&ssi_ick>; |
| clock-names = "ssi_ssr_fck", |
| "ssi_sst_fck", |
| "ssi_ick"; |
| }; |
| |
| &usb_otg_target { |
| clocks = <&hsotgusb_ick_3430es2>; |
| }; |
| |
| /include/ "omap34xx-omap36xx-clocks.dtsi" |
| /include/ "omap36xx-omap3430es2plus-clocks.dtsi" |
| /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" |
| /include/ "omap36xx-clocks.dtsi" |
