Documentation/devicetree/bindings/watchdog/mediatek,mtk-wdt.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek SoCs Watchdog timer

maintainers:
  - Matthias Brugger <matthias.bgg@gmail.com>

description:
  The watchdog supports a pre-timeout interrupt that fires
  timeout-sec/2 before the expiry.

allOf:
  - $ref: watchdog.yaml#

properties:
  compatible:
    oneOf:
      - enum:
          - mediatek,mt2712-wdt
          - mediatek,mt6589-wdt
          - mediatek,mt6735-wdt
          - mediatek,mt6795-wdt
          - mediatek,mt7986-wdt
          - mediatek,mt8183-wdt
          - mediatek,mt8186-wdt
          - mediatek,mt8188-wdt
          - mediatek,mt8192-wdt
          - mediatek,mt8195-wdt
      - items:
          - enum:
              - mediatek,mt2701-wdt
              - mediatek,mt6582-wdt
              - mediatek,mt6797-wdt
              - mediatek,mt7622-wdt
              - mediatek,mt7623-wdt
              - mediatek,mt7629-wdt
              - mediatek,mt8173-wdt
              - mediatek,mt8365-wdt
              - mediatek,mt8516-wdt
          - const: mediatek,mt6589-wdt

  reg:
    maxItems: 1

  interrupts:
    items:
      - description: Watchdog pre-timeout (bark) interrupt

  mediatek,disable-extrst:
    description: Disable sending output reset signal
    type: boolean

  mediatek,reset-by-toprgu:
    description: The Top Reset Generation Unit (TOPRGU) generates reset signals
      and distributes them to each IP. If present, the watchdog timer will be
      reset by TOPRGU once system resets.
    type: boolean

  '#reset-cells':
    const: 1

required:
  - compatible
  - reg

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        watchdog: watchdog@10007000 {
            compatible = "mediatek,mt8183-wdt";
            reg = <0 0x10007000 0 0x100>;
            interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
            mediatek,disable-extrst;
            timeout-sec = <10>;
            #reset-cells = <1>;
        };
    };