| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2018 Bang & Olufsen |
| */ |
| |
| #include "imx8mm.dtsi" |
| #include <dt-bindings/phy/phy-imx8-pcie.h> |
| |
| / { |
| reg_modem: regulator-modem { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_modem_regulator>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "epdev_on"; |
| gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-always-on; |
| }; |
| |
| reg_3v3_out: regulator-3v3-out { |
| compatible = "regulator-fixed"; |
| regulator-name = "3V3_OUT"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| |
| &cpu_alert0 { |
| temperature = <95000>; |
| }; |
| |
| &cpu_crit0 { |
| temperature = <105000>; |
| }; |
| |
| &ddrc { |
| operating-points-v2 = <&ddrc_opp_table>; |
| |
| ddrc_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-25000000 { |
| opp-hz = /bits/ 64 <25000000>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| }; |
| |
| opp-600000000 { |
| opp-hz = /bits/ 64 <600000000>; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| pinctrl-1 = <&pinctrl_i2c1_gpio>; |
| scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| |
| pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| rohm,reset-snvs-powered; |
| |
| regulators { |
| buck1_reg: BUCK1 { |
| regulator-name = "buck1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <850000>; |
| rohm,dvs-idle-voltage = <850000>; |
| rohm,dvs-suspend-voltage = <850000>; |
| }; |
| |
| buck2_reg: BUCK2 { |
| regulator-name = "buck2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| rohm,dvs-run-voltage = <1000000>; |
| rohm,dvs-idle-voltage = <900000>; |
| }; |
| |
| buck3_reg: BUCK3 { |
| // buck5 in datasheet |
| regulator-name = "buck3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck4_reg: BUCK4 { |
| // buck6 in datasheet |
| regulator-name = "buck4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck5_reg: BUCK5 { |
| // buck7 in datasheet |
| regulator-name = "buck5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck6_reg: BUCK6 { |
| // buck8 in datasheet |
| regulator-name = "buck6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: LDO1 { |
| regulator-name = "ldo1"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: LDO2 { |
| regulator-name = "ldo2"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: LDO3 { |
| regulator-name = "ldo3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: LDO4 { |
| regulator-name = "ldo4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo5_reg: LDO5 { |
| regulator-name = "ldo5"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| ldo6_reg: LDO6 { |
| regulator-name = "ldo6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| pinctrl-1 = <&pinctrl_i2c2_gpio>; |
| scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| &i2c3 { |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| pinctrl-1 = <&pinctrl_i2c3_gpio>; |
| scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| }; |
| |
| &pcie_phy { |
| fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; |
| fsl,tx-deemph-gen1 = <0x2d>; |
| fsl,tx-deemph-gen2 = <0xf>; |
| status = "okay"; |
| }; |
| |
| &pcie0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; |
| fsl,max-link-speed = <1>; |
| assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; |
| assigned-clock-rates = <10000000>, <250000000>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; |
| status = "okay"; |
| }; |
| |
| &uart1 { /* BT */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clk IMX8MM_CLK_UART1>; |
| assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; |
| uart-has-rtscts; |
| status = "okay"; |
| |
| bluetooth { |
| compatible = "brcm,bcm4349-bt"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_modem_bt>; |
| device-wakeup-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; |
| host-wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; |
| shutdown-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
| vbat-supply = <®_3v3_out>; |
| vddio-supply = <®_3v3_out>; |
| clocks = <&osc_32k>; |
| max-speed = <3000000>; |
| clock-names = "extclk"; |
| }; |
| }; |
| |
| &uart2 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| no-sd; |
| no-sdio; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_1 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_2 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &A53_3 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| /delete-node/ &sec_jr1; /* Job ring in use by OP-TEE */ |
| |
| &iomuxc { |
| pinctrl_i2c1: i2c1-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c1_gpio: i2c1-gpio-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3 |
| MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c2_gpio: i2c2-gpio-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3 |
| MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_i2c3_gpio: i2c3-gpio-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3 |
| MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_pcie0: pcie0-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61 |
| MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x6 |
| >; |
| }; |
| |
| pinctrl_modem_bt: modem-bt-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 |
| MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x19 |
| MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 |
| MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 |
| MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 |
| >; |
| }; |
| |
| pinctrl_modem_regulator: modem-reg-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x41 |
| >; |
| }; |
| |
| pinctrl_pmic: pmic-irq-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 |
| MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 |
| MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000190 |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000194 |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d4 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000196 |
| MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 |
| MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 |
| MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 |
| MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x1d6 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2-gpio-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_wdog: wdog-grp { |
| fsl,pins = < |
| MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
