arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * Copyright 2019 Toradex
 */

/ {
	chosen {
		stdout-path = &lpuart3;
	};

	colibri_gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpiokeys>;
		status = "disabled";

		key-wakeup {
			debounce-interval = <10>;
			gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
			label = "Wake-Up";
			linux,code = <KEY_WAKEUP>;
			wakeup-source;
		};
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

/* TODO Analogue Inputs */

/* TODO Cooling maps for DX */

&cpu_alert0 {
	hysteresis = <2000>;
	temperature = <90000>;
	type = "passive";
};

&cpu_crit0 {
	hysteresis = <2000>;
	temperature = <105000>;
	type = "critical";
};

/* TODO flexcan1 - 3 */

/* TODO GPU */

/* On-module I2C */
&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
	status = "okay";

	/* Touch controller */
	touchscreen@2c {
		compatible = "adi,ad7879-1";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_ad7879_int>;
		reg = <0x2c>;
		interrupt-parent = <&lsio_gpio3>;
		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
		touchscreen-max-pressure = <4096>;
		adi,resistance-plate-x = <120>;
		adi,first-conversion-delay = /bits/ 8 <3>;
		adi,acquisition-time = /bits/ 8 <1>;
		adi,median-filter-size = /bits/ 8 <2>;
		adi,averaging = /bits/ 8 <1>;
		adi,conversion-interval = /bits/ 8 <255>;
		status = "disabled";
	};
};

/* TODO i2c lvds0 accessible on FFC (X2) */

/* TODO i2c lvds1 accessible on FFC (X3) */

/* Colibri I2C */
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
};

&jpegdec {
	status = "okay";
};

&jpegenc {
	status = "okay";
};

/* TODO Parallel RRB */

/* Colibri UART_B */
&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
};

/* Colibri UART_C */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
};

/* Colibri UART_A */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};

/* Colibri FastEthernet */
&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			reg = <2>;
		};
	};
};

/* Colibri SPI */
&lpspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2>;
	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
};

&lsio_gpio0 {
	gpio-line-names = "",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_68",
			  "",
			  "",
			  "SODIMM_82",
			  "SODIMM_56",
			  "SODIMM_28",
			  "SODIMM_30",
			  "",
			  "SODIMM_61",
			  "SODIMM_103",
			  "",
			  "",
			  "",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_100";
};

&lsio_gpio1 {
	gpio-line-names = "SODIMM_86",
			  "SODIMM_92",
			  "SODIMM_90",
			  "SODIMM_88",
			  "",
			  "",
			  "",
			  "SODIMM_59",
			  "",
			  "SODIMM_6",
			  "SODIMM_8",
			  "",
			  "",
			  "SODIMM_2",
			  "SODIMM_4",
			  "SODIMM_34",
			  "SODIMM_32",
			  "SODIMM_63",
			  "SODIMM_55",
			  "SODIMM_33",
			  "SODIMM_35",
			  "SODIMM_36",
			  "SODIMM_38",
			  "SODIMM_21",
			  "SODIMM_19",
			  "SODIMM_140",
			  "SODIMM_142",
			  "SODIMM_196",
			  "SODIMM_194",
			  "SODIMM_186",
			  "SODIMM_188",
			  "SODIMM_138";
};

&lsio_gpio2 {
	gpio-line-names = "SODIMM_23",
			  "",
			  "",
			  "SODIMM_144";
};

&lsio_gpio3 {
	gpio-line-names = "SODIMM_96",
			  "SODIMM_75",
			  "SODIMM_37",
			  "SODIMM_29",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_69",
			  "SODIMM_71",
			  "SODIMM_73",
			  "SODIMM_77",
			  "SODIMM_89",
			  "SODIMM_93",
			  "SODIMM_95",
			  "SODIMM_99",
			  "SODIMM_105",
			  "SODIMM_107",
			  "SODIMM_98",
			  "SODIMM_102",
			  "SODIMM_104",
			  "SODIMM_106";
};

&lsio_gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "SODIMM_129",
			  "SODIMM_133",
			  "SODIMM_127",
			  "SODIMM_131",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_44",
			  "",
			  "SODIMM_76",
			  "SODIMM_31",
			  "SODIMM_47",
			  "SODIMM_190",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53";
};

&lsio_gpio5 {
	gpio-line-names = "",
			  "SODIMM_57",
			  "SODIMM_65",
			  "SODIMM_85",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_135",
			  "SODIMM_137",
			  "UNUSABLE_SODIMM_180",
			  "UNUSABLE_SODIMM_184";
};

/* Colibri PWM_B */
&lsio_pwm0 {
	#pwm-cells = <3>;
	pinctrl-0 = <&pinctrl_pwm_b>;
	pinctrl-names = "default";
};

/* Colibri PWM_C */
&lsio_pwm1 {
	#pwm-cells = <3>;
	pinctrl-0 = <&pinctrl_pwm_c>;
	pinctrl-names = "default";
};

/* Colibri PWM_D */
&lsio_pwm2 {
	#pwm-cells = <3>;
	pinctrl-0 = <&pinctrl_pwm_d>;
	pinctrl-names = "default";
};

/* TODO MIPI CSI */

/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */

/* TODO on-module PCIe for Wi-Fi */

/* TODO On-module i2s / Audio */

/* On-module eMMC */
&usdhc1 {
	bus-width = <8>;
	non-removable;
	no-sd;
	no-sdio;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	status = "okay";
};

/* Colibri SD/MMC Card */
&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
	vmmc-supply = <&reg_module_3v3>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
	disable-wp;
	no-1-8-v;
};

/* TODO USB Client/Host */

/* TODO USB Host */

/* TODO VPU Encoder/Decoder */

&iomuxc {
	/* On-module touch pen-down interrupt */
	pinctrl_ad7879_int: ad7879intgrp {
		fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x21>;
	};

	/* Colibri Analogue Inputs */
	pinctrl_adc0: adc0grp {
		fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60>,		/* SODIMM   8 */
			   <IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60>,		/* SODIMM   6 */
			   <IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60>,		/* SODIMM   4 */
			   <IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60>;		/* SODIMM   2 */
	};

	/* Atmel MXT touchsceen + Capacitive Touch Adapter */
	/* NOTE: This pingroup conflicts with pingroups
	 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
	 * simultaneously.
	 */
	pinctrl_atmel_adap: atmeladaptergrp {
		fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22			0x21>,		/* SODIMM  30 */
			   <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21			0x4000021>;	/* SODIMM  28 */
	};

	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
	pinctrl_atmel_conn: atmelconnectorgrp {
		fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x4000021>,	/* SODIMM 107 */
			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x21>;		/* SODIMM 106 */
	};

	pinctrl_can_int: canintgrp {
		fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40>;		/* SODIMM  73 */
	};

	pinctrl_csi_ctl: csictlgrp {
		fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20>,		/* SODIMM  77 */
			   <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20>;		/* SODIMM  89 */
	};

	pinctrl_csi_mclk: csimclkgrp {
		fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK				0xC0000041>;	/* SODIMM  75 / X3-12 */
	};

	pinctrl_ext_io0: extio0grp {
		fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08		0x06000040>;	/* SODIMM 135 */
	};

	/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
	pinctrl_fec1: fec1grp {
		fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000020>,
			   <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020>,
			   <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61>,
			   <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061>,
			   <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61>,
			   <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61>,
			   <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61>,
			   <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61>,
			   <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61>,
			   <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x61>;
	};

	pinctrl_fec1_sleep: fec1slpgrp {
		fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11			0x06000041>,
			   <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10			0x06000041>,
			   <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x41>,
			   <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41>,
			   <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x41>,
			   <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x41>,
			   <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x41>,
			   <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x41>,
			   <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x41>,
			   <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x41>;
	};

	/* Colibri optional CAN on UART_B RTS/CTS */
	pinctrl_flexcan1: flexcan0grp {
		fsl,pins = <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21>,		/* SODIMM  32 */
			   <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21>;		/* SODIMM  34 */
	};

	/* Colibri optional CAN on PS2 */
	pinctrl_flexcan2: flexcan1grp {
		fsl,pins = <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21>,		/* SODIMM  55 */
			   <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21>;		/* SODIMM  63 */
	};

	/* Colibri optional CAN on UART_A TXD/RXD */
	pinctrl_flexcan3: flexcan2grp {
		fsl,pins = <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21>,		/* SODIMM  35 */
			   <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21>;		/* SODIMM  33 */
	};

	/* Colibri LCD Back-Light GPIO */
	pinctrl_gpio_bl_on: gpioblongrp {
		fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60>;		/* SODIMM  71 */
	};

	/* HDMI Hot Plug Detect on FFC (X2) */
	pinctrl_gpio_hpd: gpiohpdgrp {
		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31		0x20>;		/* SODIMM 138 */
	};

	pinctrl_gpiokeys: gpiokeysgrp {
		fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041>;	/* SODIMM  45 */
	};

	pinctrl_hog0: hog0grp {
		fsl,pins = <IMX8QXP_CSI_D07_CI_PI_D09				0x61>,		/* SODIMM  65 */
			   <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20>,		/* SODIMM  69 */
			   <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26			0x20>,		/* SODIMM  79 */
			   <IMX8QXP_CSI_D02_CI_PI_D04				0x61>,		/* SODIMM  79 */
			   <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020>,	/* SODIMM  85 */
			   <IMX8QXP_CSI_D06_CI_PI_D08				0x61>,		/* SODIMM  85 */
			   <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17			0x20>,		/* SODIMM  95 */
			   <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27			0x20>,		/* SODIMM  97 */
			   <IMX8QXP_CSI_D03_CI_PI_D05				0x61>,		/* SODIMM  97 */
			   <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20>,		/* SODIMM  99 */
			   <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28			0x20>,		/* SODIMM 101 */
			   <IMX8QXP_CSI_D00_CI_PI_D02				0x61>,		/* SODIMM 101 */
			   <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20>,		/* SODIMM 103 */
			   <IMX8QXP_CSI_D01_CI_PI_D03				0x61>,		/* SODIMM 103 */
			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */
			   <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05			0x20>,		/* SODIMM 127 */
			   <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06			0x20>,		/* SODIMM 131 */
			   <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04			0x20>,		/* SODIMM 133 */
			   <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00			0x20>,		/* SODIMM  96 */
			   <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20>,		/* SODIMM  98 */
			   <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31			0x20>,		/* SODIMM 100 */
			   <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20>,		/* SODIMM 102 */
			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>;		/* SODIMM 104 */
	};

	pinctrl_hog1: hog1grp {
		fsl,pins = <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16			0x20>;		/* SODIMM  93 */
	};

	pinctrl_hog2: hog2grp {
		fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01			0x20>;		/* SODIMM  75 */
	};

	/*
	 * This pin is used in the SCFW as a UART. Using it from
	 * Linux would require rewritting the SCFW board file.
	 */
	pinctrl_hog_scfw: hogscfwgrp {
		fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20>;		/* SODIMM 144 */
	};

	/* On Module I2C */
	pinctrl_i2c0: i2c0grp {
		fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL		0x06000021>,
			   <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA		0x06000021>;
	};

	/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
	pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
		fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc6000020>,	/* SODIMM 140 */
			   <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc6000020>;	/* SODIMM 142 */
	};

	/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
	pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
		fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc6000020>,	/* SODIMM 186 */
			   <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc6000020>;	/* SODIMM 188 */
	};

	/* Colibri I2C */
	pinctrl_i2c1: i2c1grp {
		fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL		0x06000021>,	/* SODIMM 196 */
			   <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA		0x06000021>;	/* SODIMM 194 */
	};

	/* Colibri Parallel RGB LCD Interface */
	pinctrl_lcdif: lcdifgrp {
		fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK			0x60>,		/* SODIMM  56 */
			   <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC			0x60>,		/* SODIMM  68 */
			   <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC			0x60>,		/* SODIMM  82 */
			   <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x40>,		/* SODIMM  44 */
			   <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x40>,		/* SODIMM  44 */
			   <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00			0x60>,		/* SODIMM  76 */
			   <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21			0x60>,		/* SODIMM  76 */
			   <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01			0x60>,		/* SODIMM  70 */
			   <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02			0x60>,		/* SODIMM  60 */
			   <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03			0x60>,		/* SODIMM  58 */
			   <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04			0x60>,		/* SODIMM  78 */
			   <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05			0x60>,		/* SODIMM  72 */
			   <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60>,		/* SODIMM  80 */
			   <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60>,		/* SODIMM  46 */
			   <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60>,		/* SODIMM  62 */
			   <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60>,		/* SODIMM  48 */
			   <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10			0x60>,		/* SODIMM  74 */
			   <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11			0x60>,		/* SODIMM  50 */
			   <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60>,		/* SODIMM  52 */
			   <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60>,		/* SODIMM  54 */
			   <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60>,		/* SODIMM  66 */
			   <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60>,		/* SODIMM  64 */
			   <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60>,		/* SODIMM  57 */
			   <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01		0x60>,		/* SODIMM  57 */
			   <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17			0x60>;		/* SODIMM  61 */
	};

	/* Colibri SPI */
	pinctrl_lpspi2: lpspi2grp {
		fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00			0x21>,		/* SODIMM  86 */
			   <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040>,	/* SODIMM  92 */
			   <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040>,	/* SODIMM  90 */
			   <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040>;	/* SODIMM  88 */
	};

	pinctrl_lpspi2_cs2: lpspi2cs2grp {
		fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02		0x21>;		/* SODIMM  65 */
	};

	/* Colibri UART_B */
	pinctrl_lpuart0: lpuart0grp {
		fsl,pins = <IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020>,	/* SODIMM  36 */
			   <IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020>,	/* SODIMM  38 */
			   <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020>,	/* SODIMM  34 */
			   <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020>;	/* SODIMM  32 */
	};

	/* Colibri UART_C */
	pinctrl_lpuart2: lpuart2grp {
		fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020>,	/* SODIMM  19 */
			   <IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020>;	/* SODIMM  21 */
	};

	/* Colibri UART_A */
	pinctrl_lpuart3: lpuart3grp {
		fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX			0x06000020>,	/* SODIMM  33 */
			   <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX			0x06000020>;	/* SODIMM  35 */
	};

	/* Colibri UART_A Control */
	pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00		0x20>,		/* SODIMM  23 */
			   <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29			0x20>,		/* SODIMM  25 */
			   <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30			0x20>,		/* SODIMM  27 */
			   <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03			0x20>,		/* SODIMM  29 */
			   <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22			0x20>,		/* SODIMM  31 */
			   <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20>;		/* SODIMM  37 */
	};

	/* On module wifi module */
	pinctrl_pcieb: pciebgrp {
		fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01		0x04000061>,	/* SODIMM 178 */
			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000061>,	/* SODIMM  94 */
			   <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x60>;		/* SODIMM  81 */
	};

	/* Colibri PWM_A */
	pinctrl_pwm_a: pwmagrp {
	/* both pins are connected together, reserve the unused CSI_D05 */
		fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07				0x61>,		/* SODIMM  59 */
			   <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT			0x60>;		/* SODIMM  59 */
	};

	/* Colibri PWM_B */
	pinctrl_pwm_b: pwmbgrp {
		fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60>;		/* SODIMM  28 */
	};

	/* Colibri PWM_C */
	pinctrl_pwm_c: pwmcgrp {
		fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60>;		/* SODIMM  30 */
	};

	/* Colibri PWM_D */
	pinctrl_pwm_d: pwmdgrp {
	/* both pins are connected together, reserve the unused CSI_D04 */
		fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06				0x61>,		/* SODIMM  67 */
			   <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT			0x60>;		/* SODIMM  67 */
	};

	/* On-module I2S */
	pinctrl_sai0: sai0grp {
		fsl,pins = <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040>,
			   <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040>,
			   <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040>,
			   <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040>;
	};

	/* Colibri Audio Analogue Microphone GND */
	pinctrl_sgtl5000: sgtl5000grp {
		fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06		0x41>;
	};

	/* On-module SGTL5000 clock */
	pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
		fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0			0x21>;
	};

	/* On-module USB interrupt */
	pinctrl_usb3503a: usb3503agrp {
		fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x61>;
	};

	/* Colibri USB Client Cable Detect */
	pinctrl_usbc_det: usbcdetgrp {
		fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040>;	/* SODIMM 137 */
	};

	/* USB Host Power Enable */
	pinctrl_usbh1_reg: usbh1reggrp {
		fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03			0x06000040>;	/* SODIMM 129 */
	};

	/* On-module eMMC */
	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
	};

	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
	};

	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
		fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041>,
			   <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD			0x21>,
			   <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21>,
			   <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21>,
			   <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21>,
			   <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21>,
			   <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21>,
			   <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21>,
			   <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21>,
			   <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21>,
			   <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41>,
			   <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21>;
	};

	/* Colibri SD/MMC Card Detect */
	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
		fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021>;	/* SODIMM  43 */
	};

	pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
		fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60>;		/* SODIMM  43 */
	};

	/* Colibri SD/MMC Card */
	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041>,	/* SODIMM  47 */
			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD			0x21>,		/* SODIMM 190 */
			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21>,		/* SODIMM 192 */
			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21>,		/* SODIMM  49 */
			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21>,		/* SODIMM  51 */
			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21>,		/* SODIMM  53 */
			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
	};

	pinctrl_usdhc2_sleep: usdhc2slpgrp {
		fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23			0x60>,		/* SODIMM  47 */
			   <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24			0x60>,		/* SODIMM 190 */
			   <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60>,		/* SODIMM 192 */
			   <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60>,		/* SODIMM  49 */
			   <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60>,		/* SODIMM  51 */
			   <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60>,		/* SODIMM  53 */
			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21>;
	};

	pinctrl_wifi: wifigrp {
		fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x20>;
	};
};

/* Delete peripherals which are not present on SOC, but are defined in imx8-ss-*.dtsi */

/delete-node/ &adc1;
/delete-node/ &adc1_lpcg;
/delete-node/ &dsp;
/delete-node/ &dsp_lpcg;