arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs3 Reference Board
//
// Copyright (C) 2017 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

/dts-v1/;
#include "uniphier-pxs3.dtsi"
#include "uniphier-support-card.dtsi"

/ {
	model = "UniPhier PXs3 Reference Board";
	compatible = "socionext,uniphier-pxs3-ref", "socionext,uniphier-pxs3";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		serial2 = &serial2;
		serial3 = &serial3;
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c6 = &i2c6;
		spi0 = &spi0;
		spi1 = &spi1;
		ethernet0 = &eth0;
		ethernet1 = &eth1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0 0x80000000 0 0xa0000000>;
	};
};

&ethsc {
	interrupts = <4 8>;
};

&spi0 {
	status = "okay";
};

&spi1 {
	status = "okay";
};

&serial0 {
	status = "okay";
};

&serial2 {
	status = "okay";
};

&serial3 {
	status = "okay";
};

&gpio {
	xirq4 {
		gpio-hog;
		gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
		input;
	};
};

&i2c0 {
	status = "okay";
};

&i2c1 {
	status = "okay";
};

&i2c2 {
	status = "okay";
};

&i2c3 {
	status = "okay";
};

&sd {
	status = "okay";
};

&eth0 {
	status = "okay";
	phy-handle = <&ethphy0>;
};

&mdio0 {
	ethphy0: ethphy@0 {
		reg = <0>;
	};
};

&eth1 {
	status = "okay";
	phy-handle = <&ethphy1>;
};

&mdio1 {
	ethphy1: ethphy@0 {
		reg = <0>;
	};
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&pcie {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		reg = <0>;
	};
};

&pinctrl_ether_rgmii {
	tx {
		pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
		       "RGMII0_TXD2", "RGMII0_TXD3", "RGMII0_TXCTL";
		drive-strength = <9>;
	};
};

&pinctrl_ether1_rgmii {
	tx {
		pins = "RGMII1_TXCLK", "RGMII1_TXD0", "RGMII1_TXD1",
		       "RGMII1_TXD2", "RGMII1_TXD3", "RGMII1_TXCTL";
		drive-strength = <9>;
	};
};