| [ |
| { |
| "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", |
| "CollectPEBSRecord": "2", |
| "Counter": "35", |
| "EventName": "TOPDOWN.SLOTS", |
| "PEBScounters": "35", |
| "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).", |
| "SampleAfterValue": "10000003", |
| "Speculative": "1", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x28", |
| "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x7" |
| }, |
| { |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x28", |
| "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x18" |
| }, |
| { |
| "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x28", |
| "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.", |
| "SampleAfterValue": "200003", |
| "Speculative": "1", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Number of PREFETCHNTA instructions executed.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "SW_PREFETCH_ACCESS.NTA", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Number of PREFETCHT0 instructions executed.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "SW_PREFETCH_ACCESS.T0", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "SW_PREFETCH_ACCESS.T1_T2", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Number of PREFETCHW instructions executed.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x32", |
| "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", |
| "PEBScounters": "0,1,2,3", |
| "PublicDescription": "Counts the number of PREFETCHW instructions executed.", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xa4", |
| "EventName": "TOPDOWN.SLOTS_P", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.", |
| "SampleAfterValue": "10000003", |
| "Speculative": "1", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xa4", |
| "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.", |
| "SampleAfterValue": "10000003", |
| "Speculative": "1", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.", |
| "CollectPEBSRecord": "2", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc1", |
| "EventName": "ASSISTS.ANY", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.", |
| "SampleAfterValue": "100003", |
| "Speculative": "1", |
| "UMask": "0x7" |
| }, |
| { |
| "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x10003C0001", |
| "Offcore": "1", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x8003C0001", |
| "Offcore": "1", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts writes that generate a demand reads for ownership (RFO) request and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x10003C0002", |
| "Offcore": "1", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts streaming stores that have any type of response.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x10800", |
| "Offcore": "1", |
| "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| } |
| ] |
