Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microsemi Ocelot SoC ICPU Interrupt Controller

maintainers:
  - Alexandre Belloni <alexandre.belloni@bootlin.com>

allOf:
  - $ref: /schemas/interrupt-controller.yaml#

description: |
  the Microsemi Ocelot interrupt controller that is part of the
  ICPU. It is connected directly to the MIPS core interrupt
  controller.

properties:
  compatible:
    items:
      - enum:
          - mscc,jaguar2-icpu-intr
          - mscc,luton-icpu-intr
          - mscc,ocelot-icpu-intr
          - mscc,serval-icpu-intr


  '#interrupt-cells':
    const: 1

  '#address-cells':
    const: 0

  interrupt-controller: true

  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

required:
  - compatible
  - '#interrupt-cells'
  - '#address-cells'
  - interrupt-controller
  - reg

additionalProperties: false

examples:
  - |
    intc: interrupt-controller@70000070 {
        compatible = "mscc,ocelot-icpu-intr";
        reg = <0x70000070 0x70>;
        #interrupt-cells = <1>;
        #address-cells = <0>;
        interrupt-controller;
        interrupt-parent = <&cpuintc>;
        interrupts = <2>;
    };
...