| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2020, Konrad Dybcio |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sdm660.h> |
| #include <dt-bindings/clock/qcom,rpmcc.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PERF_CPU_SLEEP_0 |
| &PERF_CPU_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_0 |
| &PERF_CLUSTER_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1126>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_1>; |
| L2_1: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU1: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PERF_CPU_SLEEP_0 |
| &PERF_CPU_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_0 |
| &PERF_CLUSTER_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1126>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| CPU2: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PERF_CPU_SLEEP_0 |
| &PERF_CPU_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_0 |
| &PERF_CLUSTER_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1126>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| CPU3: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PERF_CPU_SLEEP_0 |
| &PERF_CPU_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_0 |
| &PERF_CLUSTER_SLEEP_1 |
| &PERF_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1126>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| CPU4: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PWR_CPU_SLEEP_0 |
| &PWR_CPU_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_0 |
| &PWR_CLUSTER_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| }; |
| |
| CPU5: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PWR_CPU_SLEEP_0 |
| &PWR_CPU_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_0 |
| &PWR_CLUSTER_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU6: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PWR_CPU_SLEEP_0 |
| &PWR_CPU_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_0 |
| &PWR_CLUSTER_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU7: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| cpu-idle-states = <&PWR_CPU_SLEEP_0 |
| &PWR_CPU_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_0 |
| &PWR_CLUSTER_SLEEP_1 |
| &PWR_CLUSTER_SLEEP_2>; |
| capacity-dmips-mhz = <1024>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU4>; |
| }; |
| |
| core1 { |
| cpu = <&CPU5>; |
| }; |
| |
| core2 { |
| cpu = <&CPU6>; |
| }; |
| |
| core3 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| PWR_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "pwr-retention"; |
| arm,psci-suspend-param = <0x40000002>; |
| entry-latency-us = <338>; |
| exit-latency-us = <423>; |
| min-residency-us = <200>; |
| }; |
| |
| PWR_CPU_SLEEP_1: cpu-sleep-0-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "pwr-power-collapse"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <515>; |
| exit-latency-us = <1821>; |
| min-residency-us = <1000>; |
| local-timer-stop; |
| }; |
| |
| PERF_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "perf-retention"; |
| arm,psci-suspend-param = <0x40000002>; |
| entry-latency-us = <154>; |
| exit-latency-us = <87>; |
| min-residency-us = <200>; |
| }; |
| |
| PERF_CPU_SLEEP_1: cpu-sleep-1-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "perf-power-collapse"; |
| arm,psci-suspend-param = <0x40000003>; |
| entry-latency-us = <262>; |
| exit-latency-us = <301>; |
| min-residency-us = <1000>; |
| local-timer-stop; |
| }; |
| |
| PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "pwr-cluster-dynamic-retention"; |
| arm,psci-suspend-param = <0x400000F2>; |
| entry-latency-us = <284>; |
| exit-latency-us = <384>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| |
| PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "pwr-cluster-retention"; |
| arm,psci-suspend-param = <0x400000F3>; |
| entry-latency-us = <338>; |
| exit-latency-us = <423>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| |
| PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "pwr-cluster-retention"; |
| arm,psci-suspend-param = <0x400000F4>; |
| entry-latency-us = <515>; |
| exit-latency-us = <1821>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| |
| PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "perf-cluster-dynamic-retention"; |
| arm,psci-suspend-param = <0x400000F2>; |
| entry-latency-us = <272>; |
| exit-latency-us = <329>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| |
| PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "perf-cluster-retention"; |
| arm,psci-suspend-param = <0x400000F3>; |
| entry-latency-us = <332>; |
| exit-latency-us = <368>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| |
| PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "perf-cluster-retention"; |
| arm,psci-suspend-param = <0x400000F4>; |
| entry-latency-us = <545>; |
| exit-latency-us = <1609>; |
| min-residency-us = <9987>; |
| local-timer-stop; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-msm8998", "qcom,scm"; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the reg */ |
| reg = <0 0 0 0>; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| wlan_msa_guard: wlan-msa-guard@85600000 { |
| reg = <0x0 0x85600000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| wlan_msa_mem: wlan-msa-mem@85700000 { |
| reg = <0x0 0x85700000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| qhee_code: qhee-code@85800000 { |
| reg = <0x0 0x85800000 0x0 0x3700000>; |
| no-map; |
| }; |
| |
| smem_region: smem-mem@86000000 { |
| reg = <0 0x86000000 0 0x200000>; |
| no-map; |
| }; |
| |
| tz_mem: memory@86200000 { |
| reg = <0x0 0x86200000 0x0 0x3300000>; |
| no-map; |
| }; |
| |
| modem_fw_mem: modem-fw-region@8ac00000 { |
| reg = <0x0 0x8ac00000 0x0 0x7e00000>; |
| no-map; |
| }; |
| |
| adsp_fw_mem: adsp-fw-region@92a00000 { |
| reg = <0x0 0x92a00000 0x0 0x1e00000>; |
| no-map; |
| }; |
| |
| pil_mba_mem: pil-mba-region@94800000 { |
| reg = <0x0 0x94800000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| buffer_mem: buffer-region@94a00000 { |
| reg = <0x0 0x94a00000 0x0 0x100000>; |
| no-map; |
| }; |
| |
| venus_fw_mem: venus-fw-region@9f800000 { |
| reg = <0x0 0x9f800000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| secure_region2: secure-region2@f7c00000 { |
| reg = <0x0 0xf7c00000 0x0 0x5c00000>; |
| no-map; |
| }; |
| |
| adsp_mem: adsp-region@f6000000 { |
| reg = <0x0 0xf6000000 0x0 0x800000>; |
| no-map; |
| }; |
| |
| qseecom_ta_mem: qseecom-ta-region@fec00000 { |
| reg = <0x0 0xfec00000 0x0 0x1000000>; |
| no-map; |
| }; |
| |
| qseecom_mem: qseecom-region@f6800000 { |
| reg = <0x0 0xf6800000 0x0 0x1400000>; |
| no-map; |
| }; |
| |
| secure_display_memory: secure-region@f5c00000 { |
| reg = <0x0 0xf5c00000 0x0 0x5c00000>; |
| no-map; |
| }; |
| |
| cont_splash_mem: cont-splash-region@9d400000 { |
| reg = <0x0 0x9d400000 0x0 0x23ff000>; |
| no-map; |
| }; |
| }; |
| |
| rpm-glink { |
| compatible = "qcom,glink-rpm"; |
| |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| mboxes = <&apcs_glb 0>; |
| |
| rpm_requests: rpm-requests { |
| compatible = "qcom,rpm-sdm660"; |
| qcom,glink-channels = "rpm_requests"; |
| |
| rpmcc: clock-controller { |
| compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; |
| #clock-cells = <1>; |
| }; |
| }; |
| }; |
| |
| smem: smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_region>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm630"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x00100000 0x94000>; |
| |
| clock-names = "xo", "sleep_clk"; |
| clocks = <&xo_board>, |
| <&sleep_clk>; |
| }; |
| |
| rpm_msg_ram: memory@778000 { |
| compatible = "qcom,rpm-msg-ram"; |
| reg = <0x00778000 0x7000>; |
| }; |
| |
| qfprom: qfprom@780000 { |
| compatible = "qcom,qfprom"; |
| reg = <0x00780000 0x621c>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| rng: rng@793000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0x00793000 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| restart@10ac000 { |
| compatible = "qcom,pshold"; |
| reg = <0x010ac000 0x4>; |
| }; |
| |
| anoc2_smmu: iommu@16c0000 { |
| compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; |
| reg = <0x016c0000 0x40000>; |
| #iommu-cells = <1>; |
| |
| #global-interrupts = <2>; |
| interrupts = |
| <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| |
| <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| }; |
| |
| tcsr_mutex_regs: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0x01f40000 0x20000>; |
| }; |
| |
| tlmm: pinctrl@3000000 { |
| compatible = "qcom,sdm630-pinctrl"; |
| reg = <0x03000000 0xc00000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <0x2>; |
| interrupt-controller; |
| #interrupt-cells = <0x2>; |
| |
| blsp1_uart1_default: blsp1-uart1-default { |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_uart1_sleep: blsp1-uart1-sleep { |
| pins = "gpio0", "gpio1", "gpio2", "gpio3"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp1_uart2_default: blsp1-uart2-default { |
| pins = "gpio4", "gpio5"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_uart1_tx_active: blsp2-uart1-tx-active { |
| pins = "gpio16"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep { |
| pins = "gpio16"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active { |
| pins = "gpio17", "gpio18"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep { |
| pins = "gpio17", "gpio18"; |
| drive-strength = <2>; |
| bias-no-pull; |
| }; |
| |
| blsp2_uart1_rfr_active: blsp2-uart1-rfr-active { |
| pins = "gpio19"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep { |
| pins = "gpio19"; |
| drive-strength = <2>; |
| bias-no-pull; |
| }; |
| |
| i2c1_default: i2c1-default { |
| pins = "gpio2", "gpio3"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c1_sleep: i2c1-sleep { |
| pins = "gpio2", "gpio3"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c2_default: i2c2-default { |
| pins = "gpio6", "gpio7"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c2_sleep: i2c2-sleep { |
| pins = "gpio6", "gpio7"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c3_default: i2c3-default { |
| pins = "gpio10", "gpio11"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c3_sleep: i2c3-sleep { |
| pins = "gpio10", "gpio11"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c4_default: i2c4-default { |
| pins = "gpio14", "gpio15"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c4_sleep: i2c4-sleep { |
| pins = "gpio14", "gpio15"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c5_default: i2c5-default { |
| pins = "gpio18", "gpio19"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c5_sleep: i2c5-sleep { |
| pins = "gpio18", "gpio19"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c6_default: i2c6-default { |
| pins = "gpio22", "gpio23"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c6_sleep: i2c6-sleep { |
| pins = "gpio22", "gpio23"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c7_default: i2c7-default { |
| pins = "gpio26", "gpio27"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c7_sleep: i2c7-sleep { |
| pins = "gpio26", "gpio27"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| i2c8_default: i2c8-default { |
| pins = "gpio30", "gpio31"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| |
| i2c8_sleep: i2c8-sleep { |
| pins = "gpio30", "gpio31"; |
| drive-strength = <2>; |
| bias-pull-up; |
| }; |
| |
| sdc1_clk_on: sdc1-clk-on { |
| pins = "sdc1_clk"; |
| bias-disable; |
| drive-strength = <16>; |
| }; |
| |
| sdc1_clk_off: sdc1-clk-off { |
| pins = "sdc1_clk"; |
| bias-disable; |
| drive-strength = <2>; |
| }; |
| |
| sdc1_cmd_on: sdc1-cmd-on { |
| pins = "sdc1_cmd"; |
| bias-pull-up; |
| drive-strength = <10>; |
| }; |
| |
| sdc1_cmd_off: sdc1-cmd-off { |
| pins = "sdc1_cmd"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| sdc1_data_on: sdc1-data-on { |
| pins = "sdc1_data"; |
| bias-pull-up; |
| drive-strength = <8>; |
| }; |
| |
| sdc1_data_off: sdc1-data-off { |
| pins = "sdc1_data"; |
| bias-pull-up; |
| drive-strength = <2>; |
| }; |
| |
| sdc1_rclk_on: sdc1-rclk-on { |
| pins = "sdc1_rclk"; |
| bias-pull-down; |
| }; |
| |
| sdc1_rclk_off: sdc1-rclk-off { |
| pins = "sdc1_rclk"; |
| bias-pull-down; |
| }; |
| }; |
| |
| kgsl_smmu: iommu@5040000 { |
| compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; |
| reg = <0x05040000 0x10000>; |
| #iommu-cells = <1>; |
| |
| #global-interrupts = <2>; |
| interrupts = |
| <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| }; |
| |
| lpass_smmu: iommu@5100000 { |
| compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; |
| reg = <0x05100000 0x40000>; |
| #iommu-cells = <1>; |
| |
| #global-interrupts = <2>; |
| interrupts = |
| <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| |
| <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| }; |
| |
| spmi_bus: spmi@800f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x0800f000 0x1000>, |
| <0x08400000 0x1000000>, |
| <0x09400000 0x1000000>, |
| <0x0a400000 0x220000>, |
| <0x0800a000 0x3000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| sdhc_1: sdhci@c0c4000 { |
| compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0x0c0c4000 0x1000>, |
| <0x0c0c5000 0x1000>, |
| <0x0c0c8000 0x8000>; |
| reg-names = "hc", "cqhci", "ice"; |
| |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_APPS_CLK>, |
| <&gcc GCC_SDCC1_AHB_CLK>, |
| <&xo_board>, |
| <&gcc GCC_SDCC1_ICE_CORE_CLK>; |
| clock-names = "core", "iface", "xo", "ice"; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; |
| pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; |
| |
| bus-width = <8>; |
| non-removable; |
| |
| status = "disabled"; |
| }; |
| |
| blsp1_dma: dma-controller@c144000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x0c144000 0x1f000>; |
| interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| qcom,controlled-remotely; |
| num-channels = <18>; |
| qcom,num-ees = <4>; |
| }; |
| |
| blsp1_uart1: serial@c16f000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x0c16f000 0x200>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp1_uart1_default>; |
| pinctrl-1 = <&blsp1_uart1_sleep>; |
| status = "disabled"; |
| }; |
| |
| blsp1_uart2: serial@c170000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x0c170000 0x1000>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&blsp1_uart2_default>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c1: i2c@c175000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c175000 0x600>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c1_default>; |
| pinctrl-1 = <&i2c1_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c2: i2c@c176000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c176000 0x600>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c2_default>; |
| pinctrl-1 = <&i2c2_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c3: i2c@c177000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c177000 0x600>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c3_default>; |
| pinctrl-1 = <&i2c3_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c4: i2c@c178000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c178000 0x600>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c4_default>; |
| pinctrl-1 = <&i2c4_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp2_dma: dma-controller@c184000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x0c184000 0x1f000>; |
| interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| qcom,controlled-remotely; |
| num-channels = <18>; |
| qcom,num-ees = <4>; |
| }; |
| |
| blsp2_uart1: serial@c1af000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x0c1af000 0x200>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active |
| &blsp2_uart1_rfr_active>; |
| pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep |
| &blsp2_uart1_rfr_sleep>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c5: i2c@c1b5000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c1b5000 0x600>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c5_default>; |
| pinctrl-1 = <&i2c5_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c6: i2c@c1b6000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c1b6000 0x600>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c6_default>; |
| pinctrl-1 = <&i2c6_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c7: i2c@c1b7000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c1b7000 0x600>; |
| interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c7_default>; |
| pinctrl-1 = <&i2c7_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| blsp_i2c8: i2c@c1b8000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| reg = <0x0c1b8000 0x600>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&i2c8_default>; |
| pinctrl-1 = <&i2c8_sleep>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| mmss_smmu: iommu@cd00000 { |
| compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; |
| reg = <0x0cd00000 0x40000>; |
| #iommu-cells = <1>; |
| |
| #global-interrupts = <2>; |
| interrupts = |
| <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
| |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| }; |
| |
| apcs_glb: mailbox@17911000 { |
| compatible = "qcom,sdm660-apcs-hmss-global"; |
| reg = <0x17911000 0x1000>; |
| |
| #mbox-cells = <1>; |
| }; |
| |
| timer@17920000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17920000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@17921000 { |
| frame-number = <0>; |
| interrupts = <0 8 0x4>, |
| <0 7 0x4>; |
| reg = <0x17921000 0x1000>, |
| <0x17922000 0x1000>; |
| }; |
| |
| frame@17923000 { |
| frame-number = <1>; |
| interrupts = <0 9 0x4>; |
| reg = <0x17923000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17924000 { |
| frame-number = <2>; |
| interrupts = <0 10 0x4>; |
| reg = <0x17924000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17925000 { |
| frame-number = <3>; |
| interrupts = <0 11 0x4>; |
| reg = <0x17925000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17926000 { |
| frame-number = <4>; |
| interrupts = <0 12 0x4>; |
| reg = <0x17926000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17927000 { |
| frame-number = <5>; |
| interrupts = <0 13 0x4>; |
| reg = <0x17927000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17928000 { |
| frame-number = <6>; |
| interrupts = <0 14 0x4>; |
| reg = <0x17928000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17b00000 0x100000>; /* GICR * 8 */ |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_regs 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 0xf08>, |
| <GIC_PPI 2 0xf08>, |
| <GIC_PPI 3 0xf08>, |
| <GIC_PPI 0 0xf08>; |
| }; |
| }; |
| |
