| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2018, Craig Tatlor. |
| * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm660.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| chosen { }; |
| |
| clocks { |
| xo_board: xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| next-level-cache = <&L2_1>; |
| L2_1: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| L1_I_100: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_100: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU1: cpu@101 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| next-level-cache = <&L2_1>; |
| L1_I_101: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_101: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU2: cpu@102 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| next-level-cache = <&L2_1>; |
| L1_I_102: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_102: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU3: cpu@103 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| next-level-cache = <&L2_1>; |
| L1_I_103: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_103: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU4: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <640>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| L1_I_0: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_0: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU5: cpu@1 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <640>; |
| next-level-cache = <&L2_0>; |
| L1_I_1: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_1: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU6: cpu@2 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <640>; |
| next-level-cache = <&L2_0>; |
| L1_I_2: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_2: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| CPU7: cpu@3 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo260"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <640>; |
| next-level-cache = <&L2_0>; |
| L1_I_3: l1-icache { |
| compatible = "cache"; |
| }; |
| L1_D_3: l1-dcache { |
| compatible = "cache"; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU4>; |
| }; |
| |
| core1 { |
| cpu = <&CPU5>; |
| }; |
| |
| core2 { |
| cpu = <&CPU6>; |
| }; |
| |
| core3 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm"; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the reg */ |
| reg = <0 0 0 0>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm660"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| reg = <0x00100000 0x94000>; |
| }; |
| |
| tlmm: pinctrl@3100000 { |
| compatible = "qcom,sdm660-pinctrl"; |
| reg = <0x03100000 0x400000>, |
| <0x03500000 0x400000>, |
| <0x03900000 0x400000>; |
| reg-names = "south", "center", "north"; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&tlmm 0 0 114>; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| |
| uart_console_active: uart_console_active { |
| pinmux { |
| pins = "gpio4", "gpio5"; |
| function = "blsp_uart2"; |
| }; |
| |
| pinconf { |
| pins = "gpio4", "gpio5"; |
| drive-strength = <2>; |
| bias-disable; |
| }; |
| }; |
| }; |
| |
| spmi_bus: spmi@800f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x0800f000 0x1000>, |
| <0x08400000 0x1000000>, |
| <0x09400000 0x1000000>, |
| <0x0a400000 0x220000>, |
| <0x0800a000 0x3000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| blsp1_uart2: serial@c170000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x0c170000 0x1000>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| timer@17920000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17920000 0x1000>; |
| |
| frame@17921000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17921000 0x1000>, |
| <0x17922000 0x1000>; |
| }; |
| |
| frame@17923000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17923000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17924000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17924000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17925000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17925000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17926000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17926000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17927000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17927000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17928000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17928000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x17a00000 0x10000>, |
| <0x17b00000 0x100000>; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| }; |
