| [ |
| { |
| "MetricName": "branch_misprediction_ratio", |
| "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)", |
| "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)", |
| "MetricGroup": "branch_prediction", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "EventName": "all_dc_accesses", |
| "EventCode": "0x29", |
| "BriefDescription": "All L1 Data Cache Accesses", |
| "UMask": "0x07" |
| }, |
| { |
| "MetricName": "all_l2_cache_accesses", |
| "BriefDescription": "All L2 Cache Accesses", |
| "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", |
| "MetricGroup": "l2_cache" |
| }, |
| { |
| "EventName": "l2_cache_accesses_from_ic_misses", |
| "EventCode": "0x60", |
| "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)", |
| "UMask": "0x10" |
| }, |
| { |
| "EventName": "l2_cache_accesses_from_dc_misses", |
| "EventCode": "0x60", |
| "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)", |
| "UMask": "0xc8" |
| }, |
| { |
| "MetricName": "l2_cache_accesses_from_l2_hwpf", |
| "BriefDescription": "L2 Cache Accesses from L2 HWPF", |
| "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", |
| "MetricGroup": "l2_cache" |
| }, |
| { |
| "MetricName": "all_l2_cache_misses", |
| "BriefDescription": "All L2 Cache Misses", |
| "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", |
| "MetricGroup": "l2_cache" |
| }, |
| { |
| "EventName": "l2_cache_misses_from_ic_miss", |
| "EventCode": "0x64", |
| "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses", |
| "UMask": "0x01" |
| }, |
| { |
| "EventName": "l2_cache_misses_from_dc_misses", |
| "EventCode": "0x64", |
| "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses", |
| "UMask": "0x08" |
| }, |
| { |
| "MetricName": "l2_cache_misses_from_l2_hwpf", |
| "BriefDescription": "L2 Cache Misses from L2 HWPF", |
| "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3", |
| "MetricGroup": "l2_cache" |
| }, |
| { |
| "MetricName": "all_l2_cache_hits", |
| "BriefDescription": "All L2 Cache Hits", |
| "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2", |
| "MetricGroup": "l2_cache" |
| }, |
| { |
| "EventName": "l2_cache_hits_from_ic_misses", |
| "EventCode": "0x64", |
| "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses", |
| "UMask": "0x06" |
| }, |
| { |
| "EventName": "l2_cache_hits_from_dc_misses", |
| "EventCode": "0x64", |
| "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses", |
| "UMask": "0x70" |
| }, |
| { |
| "EventName": "l2_cache_hits_from_l2_hwpf", |
| "EventCode": "0x70", |
| "BriefDescription": "L2 Cache Hits from L2 HWPF", |
| "UMask": "0xff" |
| }, |
| { |
| "EventName": "l3_accesses", |
| "EventCode": "0x04", |
| "BriefDescription": "L3 Accesses", |
| "UMask": "0xff", |
| "Unit": "L3PMC" |
| }, |
| { |
| "EventName": "l3_misses", |
| "EventCode": "0x04", |
| "BriefDescription": "L3 Misses (includes Chg2X)", |
| "UMask": "0x01", |
| "Unit": "L3PMC" |
| }, |
| { |
| "MetricName": "l3_read_miss_latency", |
| "BriefDescription": "Average L3 Read Miss Latency (in core clocks)", |
| "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs", |
| "MetricGroup": "l3_cache", |
| "ScaleUnit": "1core clocks" |
| }, |
| { |
| "MetricName": "ic_fetch_miss_ratio", |
| "BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio", |
| "MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss)", |
| "MetricGroup": "l2_cache", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "l1_itlb_misses", |
| "BriefDescription": "L1 ITLB Misses", |
| "MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_miss", |
| "MetricGroup": "tlb" |
| }, |
| { |
| "EventName": "l2_itlb_misses", |
| "EventCode": "0x85", |
| "BriefDescription": "L2 ITLB Misses & Instruction page walks", |
| "UMask": "0x07" |
| }, |
| { |
| "EventName": "l1_dtlb_misses", |
| "EventCode": "0x45", |
| "BriefDescription": "L1 DTLB Misses", |
| "UMask": "0xff" |
| }, |
| { |
| "EventName": "l2_dtlb_misses", |
| "EventCode": "0x45", |
| "BriefDescription": "L2 DTLB Misses & Data page walks", |
| "UMask": "0xf0" |
| }, |
| { |
| "EventName": "all_tlbs_flushed", |
| "EventCode": "0x78", |
| "BriefDescription": "All TLBs Flushed", |
| "UMask": "0xdf" |
| }, |
| { |
| "EventName": "uops_dispatched", |
| "EventCode": "0xaa", |
| "BriefDescription": "Micro-ops Dispatched", |
| "UMask": "0x03" |
| }, |
| { |
| "EventName": "sse_avx_stalls", |
| "EventCode": "0x0e", |
| "BriefDescription": "Mixed SSE/AVX Stalls", |
| "UMask": "0x0e" |
| }, |
| { |
| "EventName": "uops_retired", |
| "EventCode": "0xc1", |
| "BriefDescription": "Micro-ops Retired" |
| }, |
| { |
| "MetricName": "all_remote_links_outbound", |
| "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)", |
| "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3", |
| "MetricGroup": "data_fabric", |
| "PerPkg": "1", |
| "ScaleUnit": "3e-5MiB" |
| }, |
| { |
| "MetricName": "nps1_die_to_dram", |
| "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die)", |
| "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7", |
| "MetricConstraint": "NO_GROUP_EVENTS", |
| "MetricGroup": "data_fabric", |
| "PerPkg": "1", |
| "ScaleUnit": "6.1e-5MiB" |
| } |
| ] |