tools/perf/pmu-events/arch/x86/amdzen5/execution.json

[
  {
    "EventName": "ex_ret_instr",
    "EventCode": "0xc0",
    "BriefDescription": "Retired instructions."
  },
  {
    "EventName": "ex_ret_ops",
    "EventCode": "0xc1",
    "BriefDescription": "Retired macro-ops."
  },
  {
    "EventName": "ex_ret_brn",
    "EventCode": "0xc2",
    "BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
  },
  {
    "EventName": "ex_ret_brn_misp",
    "EventCode": "0xc3",
    "BriefDescription": "Retired branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_brn_tkn",
    "EventCode": "0xc4",
    "BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
  },
  {
    "EventName": "ex_ret_brn_tkn_misp",
    "EventCode": "0xc5",
    "BriefDescription": "Retired taken branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_brn_far",
    "EventCode": "0xc6",
    "BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
  },
  {
    "EventName": "ex_ret_near_ret",
    "EventCode": "0xc8",
    "BriefDescription": "Retired near returns (RET or RET Iw)."
  },
  {
    "EventName": "ex_ret_near_ret_mispred",
    "EventCode": "0xc9",
    "BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
    "EventName": "ex_ret_brn_ind_misp",
    "EventCode": "0xca",
    "BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.x87",
    "EventCode": "0xcb",
    "BriefDescription": "Retired x87 instructions.",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.mmx",
    "EventCode": "0xcb",
    "BriefDescription": "Retired MMX instructions.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_ret_mmx_fp_instr.sse",
    "EventCode": "0xcb",
    "BriefDescription": "Retired SSE instructions (includes SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42 and AVX).",
    "UMask": "0x04"
  },
  {
    "EventName": "ex_ret_ind_brch_instr",
    "EventCode": "0xcc",
    "BriefDescription": "Retired indirect branch instructions."
  },
  {
    "EventName": "ex_ret_cond",
    "EventCode": "0xd1",
    "BriefDescription": "Retired conditional branch instructions."
  },
  {
    "EventName": "ex_div_busy",
    "EventCode": "0xd3",
    "BriefDescription": "Number of cycles the divider is busy."
  },
  {
    "EventName": "ex_div_count",
    "EventCode": "0xd4",
    "BriefDescription": "Divide ops executed."
  },
  {
    "EventName": "ex_no_retire.empty",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire due  to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_no_retire.not_complete",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_no_retire.other",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
    "UMask": "0x08"
  },
  {
    "EventName": "ex_no_retire.thread_not_selected",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
    "UMask": "0x10"
  },
  {
    "EventName": "ex_no_retire.load_not_complete",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
    "UMask": "0xa2"
  },
  {
    "EventName": "ex_no_retire.all",
    "EventCode": "0xd6",
    "BriefDescription": "Cycles with no retire for any reason.",
    "UMask": "0x1b"
  },
  {
    "EventName": "ex_ret_ucode_instr",
    "EventCode": "0x1c1",
    "BriefDescription": "Retired microcoded instructions."
  },
  {
    "EventName": "ex_ret_ucode_ops",
    "EventCode": "0x1c2",
    "BriefDescription": "Retired microcode ops."
  },
  {
    "EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
    "EventCode": "0x1c7",
    "BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
  },
  {
    "EventName": "ex_ret_uncond_brnch_instr_mispred",
    "EventCode": "0x1c8",
    "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
  },
  {
    "EventName": "ex_ret_uncond_brnch_instr",
    "EventCode": "0x1c9",
    "BriefDescription": "Retired unconditional branch instructions."
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops tagged by IBS.",
    "UMask": "0x01"
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops tagged by IBS that retired.",
    "UMask": "0x02"
  },
  {
    "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
    "EventCode": "0x1cf",
    "BriefDescription": "Ops not tagged by IBS due to a previous tagged op that has not yet signaled interrupt.",
    "UMask": "0x04"
  },
  {
    "EventName": "ex_ret_fused_instr",
    "EventCode": "0x1d0",
    "BriefDescription": "Retired fused instructions."
  }
]