| [ |
| { |
| "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xE6", |
| "EventName": "BACLEARS.ANY", |
| "PublicDescription": "Number of front end re-steers due to BPU misprediction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1f" |
| }, |
| { |
| "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "DSB2MITE_SWITCHES.COUNT", |
| "PublicDescription": "Number of DSB to MITE switches.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAB", |
| "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", |
| "PublicDescription": "Cycles DSB to MITE switches caused delay.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAC", |
| "EventName": "DSB_FILL.EXCEED_DSB_LINES", |
| "PublicDescription": "DSB Fill encountered > 3 DSB lines.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.HIT", |
| "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.IFETCH_STALL", |
| "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Instruction cache, streaming buffer and victim cache misses", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x80", |
| "EventName": "ICACHE.MISSES", |
| "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.", |
| "SampleAfterValue": "200003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops", |
| "Counter": "0,1,2,3", |
| "CounterMask": "4", |
| "EventCode": "0x79", |
| "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", |
| "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x18" |
| }, |
| { |
| "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", |
| "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x18" |
| }, |
| { |
| "BriefDescription": "Cycles MITE is delivering 4 Uops", |
| "Counter": "0,1,2,3", |
| "CounterMask": "4", |
| "EventCode": "0x79", |
| "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", |
| "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x24" |
| }, |
| { |
| "BriefDescription": "Cycles MITE is delivering any Uop", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", |
| "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x24" |
| }, |
| { |
| "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.DSB_CYCLES", |
| "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.DSB_UOPS", |
| "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.EMPTY", |
| "PublicDescription": "Counts cycles the IDQ is empty.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_ALL_UOPS", |
| "PublicDescription": "Number of uops delivered to IDQ from any path.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x3c" |
| }, |
| { |
| "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_CYCLES", |
| "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MITE_UOPS", |
| "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_CYCLES", |
| "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x30" |
| }, |
| { |
| "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_DSB_CYCLES", |
| "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EdgeDetect": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_DSB_OCCUR", |
| "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_DSB_UOPS", |
| "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_MITE_UOPS", |
| "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EdgeDetect": "1", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_SWITCHES", |
| "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x30" |
| }, |
| { |
| "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x79", |
| "EventName": "IDQ.MS_UOPS", |
| "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x30" |
| }, |
| { |
| "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", |
| "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", |
| "Counter": "0,1,2,3", |
| "CounterMask": "4", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", |
| "Invert": "1", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.", |
| "Counter": "0,1,2,3", |
| "CounterMask": "3", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Cycles with less than 2 uops delivered by the front end.", |
| "Counter": "0,1,2,3", |
| "CounterMask": "2", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Cycles with less than 3 uops delivered by the front end.", |
| "Counter": "0,1,2,3", |
| "CounterMask": "1", |
| "EventCode": "0x9C", |
| "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| } |
| ] |
