| [ |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x400", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "53", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "1009", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "20011", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x800", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "23", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "503", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100007", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "101", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "2003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", |
| "Counter": "0,1,2,3,4,5,6,7,8,9", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "50021", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.", |
| "Counter": "0,1", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", |
| "PEBS": "2", |
| "PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts cacheable demand data reads were not supplied by the L3 cache.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xB7", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x3FBFC00001", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x2A,0x2B", |
| "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0xFE7F8000001", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts demand reads for ownership, including SWPREFETCHW which is an RFO were not supplied by the L3 cache.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xB7", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x3FBFC00002", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x2A,0x2B", |
| "EventName": "OCR.DEMAND_RFO.L3_MISS", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0xFE7F8000002", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| } |
| ] |
