| [ |
| { |
| "BriefDescription": "DTLB load misses", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8", |
| "EventName": "DTLB_LOAD_MISSES.ANY", |
| "SampleAfterValue": "200000", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "DTLB load miss caused by low part of address", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8", |
| "EventName": "DTLB_LOAD_MISSES.PDE_MISS", |
| "SampleAfterValue": "200000", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "DTLB second level hit", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8", |
| "EventName": "DTLB_LOAD_MISSES.STLB_HIT", |
| "SampleAfterValue": "2000000", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "DTLB load miss page walks complete", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x8", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "200000", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "DTLB misses", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x49", |
| "EventName": "DTLB_MISSES.ANY", |
| "SampleAfterValue": "200000", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "DTLB first level misses but second level hit", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x49", |
| "EventName": "DTLB_MISSES.STLB_HIT", |
| "SampleAfterValue": "200000", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "DTLB miss page walks", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x49", |
| "EventName": "DTLB_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "200000", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "ITLB flushes", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xAE", |
| "EventName": "ITLB_FLUSH", |
| "SampleAfterValue": "2000000", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "ITLB miss", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.ANY", |
| "SampleAfterValue": "200000", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "ITLB miss page walks", |
| "Counter": "0,1,2,3", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "200000", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC8", |
| "EventName": "ITLB_MISS_RETIRED", |
| "PEBS": "1", |
| "SampleAfterValue": "200000", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xCB", |
| "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", |
| "PEBS": "1", |
| "SampleAfterValue": "200000", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", |
| "Counter": "0,1,2,3", |
| "EventCode": "0xC", |
| "EventName": "MEM_STORE_RETIRED.DTLB_MISS", |
| "PEBS": "1", |
| "SampleAfterValue": "200000", |
| "UMask": "0x1" |
| } |
| ] |
