| [ |
| { |
| "BriefDescription": "Counts the number of cycles when any of the floating point dividers are active.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "CounterMask": "1", |
| "EventCode": "0xcd", |
| "EventName": "ARITH.FPDIV_ACTIVE", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts the number of all types of floating point operations per uop with all default weighting", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc8", |
| "EventName": "FP_FLOPS_RETIRED.ALL", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x3" |
| }, |
| { |
| "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP64]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "Deprecated": "1", |
| "EventCode": "0xc8", |
| "EventName": "FP_FLOPS_RETIRED.DP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts the number of floating point operations that produce 32 bit single precision results [This event is alias to FP_FLOPS_RETIRED.SP]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc8", |
| "EventName": "FP_FLOPS_RETIRED.FP32", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts the number of floating point operations that produce 64 bit double precision results [This event is alias to FP_FLOPS_RETIRED.DP]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc8", |
| "EventName": "FP_FLOPS_RETIRED.FP64", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "This event is deprecated. [This event is alias to FP_FLOPS_RETIRED.FP32]", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "Deprecated": "1", |
| "EventCode": "0xc8", |
| "EventName": "FP_FLOPS_RETIRED.SP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts the total number of floating point retired instructions.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_INST_RETIRED.128B_DP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_INST_RETIRED.128B_SP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_INST_RETIRED.256B_DP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_INST_RETIRED.32B_SP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc7", |
| "EventName": "FP_INST_RETIRED.64B_DP", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc3", |
| "EventName": "MACHINE_CLEARS.FP_ASSIST", |
| "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", |
| "SampleAfterValue": "20003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "EventCode": "0xc2", |
| "EventName": "UOPS_RETIRED.FPDIV", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x8" |
| } |
| ] |
