Documentation/devicetree/bindings/spi/mediatek,spi-mtk-nor.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-nor.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Serial NOR flash controller for MediaTek ARM SoCs

maintainers:
  - Bayi Cheng <bayi.cheng@mediatek.com>
  - Chuanhong Guo <gch981213@gmail.com>

description: |
  This spi controller support single, dual, or quad mode transfer for
  SPI NOR flash. There should be only one spi slave device following
  generic spi bindings. It's not recommended to use this controller
  for devices other than SPI NOR flash due to limited transfer
  capability of this controller.

allOf:
  - $ref: /spi/spi-controller.yaml#

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - mediatek,mt2701-nor
              - mediatek,mt2712-nor
              - mediatek,mt7622-nor
              - mediatek,mt7623-nor
              - mediatek,mt7629-nor
              - mediatek,mt8192-nor
              - mediatek,mt8195-nor
          - enum:
              - mediatek,mt8173-nor
      - items:
          - const: mediatek,mt8173-nor
  reg:
    maxItems: 1

  interrupts:
    maxItems: 1

  clocks:
    items:
      - description: clock used for spi bus
      - description: clock used for controller

  clock-names:
    items:
      - const: spi
      - const: sf

required:
  - compatible
  - reg
  - interrupts
  - clocks
  - clock-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/clock/mt8173-clk.h>

    soc {
      #address-cells = <2>;
      #size-cells = <2>;

      nor_flash: spi@1100d000 {
        compatible = "mediatek,mt8173-nor";
        reg = <0 0x1100d000 0 0xe0>;
        interrupts = <&spi_flash_irq>;
        clocks = <&pericfg CLK_PERI_SPI>, <&topckgen CLK_TOP_SPINFI_IFR_SEL>;
        clock-names = "spi", "sf";
        #address-cells = <1>;
        #size-cells = <0>;

        flash@0 {
          compatible = "jedec,spi-nor";
          reg = <0>;
        };
      };
    };