drivers/interconnect/qcom/sm8650.h - linux - Git at Google

 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * SM8650 interconnect IDs
  *
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  * Copyright (c) 2023, Linaro Limited
  */

 #ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
 #define __DRIVERS_INTERCONNECT_QCOM_SM8650_H

 #define SM8650_MASTER_A1NOC_SNOC		0
 #define SM8650_MASTER_A2NOC_SNOC		1
 #define SM8650_MASTER_ANOC_PCIE_GEM_NOC		2
 #define SM8650_MASTER_APPSS_PROC		3
 #define SM8650_MASTER_CAMNOC_HF			4
 #define SM8650_MASTER_CAMNOC_ICP		5
 #define SM8650_MASTER_CAMNOC_SF			6
 #define SM8650_MASTER_CDSP_HCP			7
 #define SM8650_MASTER_CDSP_PROC			8
 #define SM8650_MASTER_CNOC_CFG			9
 #define SM8650_MASTER_CNOC_MNOC_CFG		10
 #define SM8650_MASTER_COMPUTE_NOC		11
 #define SM8650_MASTER_CRYPTO			12
 #define SM8650_MASTER_GEM_NOC_CNOC		13
 #define SM8650_MASTER_GEM_NOC_PCIE_SNOC		14
 #define SM8650_MASTER_GFX3D			15
 #define SM8650_MASTER_GIC			16
 #define SM8650_MASTER_GPU_TCU			17
 #define SM8650_MASTER_IPA			18
 #define SM8650_MASTER_LLCC			19
 #define SM8650_MASTER_LPASS_GEM_NOC		20
 #define SM8650_MASTER_LPASS_LPINOC		21
 #define SM8650_MASTER_LPASS_PROC		22
 #define SM8650_MASTER_LPIAON_NOC		23
 #define SM8650_MASTER_MDP			24
 #define SM8650_MASTER_MNOC_HF_MEM_NOC		25
 #define SM8650_MASTER_MNOC_SF_MEM_NOC		26
 #define SM8650_MASTER_MSS_PROC			27
 #define SM8650_MASTER_PCIE_0			28
 #define SM8650_MASTER_PCIE_1			29
 #define SM8650_MASTER_PCIE_ANOC_CFG		30
 #define SM8650_MASTER_QDSS_BAM			31
 #define SM8650_MASTER_QDSS_ETR			32
 #define SM8650_MASTER_QDSS_ETR_1		33
 #define SM8650_MASTER_QSPI_0			34
 #define SM8650_MASTER_QUP_1			35
 #define SM8650_MASTER_QUP_2			36
 #define SM8650_MASTER_QUP_3			37
 #define SM8650_MASTER_QUP_CORE_0		38
 #define SM8650_MASTER_QUP_CORE_1		39
 #define SM8650_MASTER_QUP_CORE_2		40
 #define SM8650_MASTER_SDCC_2			41
 #define SM8650_MASTER_SDCC_4			42
 #define SM8650_MASTER_SNOC_SF_MEM_NOC		43
 #define SM8650_MASTER_SP			44
 #define SM8650_MASTER_SYS_TCU			45
 #define SM8650_MASTER_UBWC_P			46
 #define SM8650_MASTER_UBWC_P_TCU		47
 #define SM8650_MASTER_UFS_MEM			48
 #define SM8650_MASTER_USB3_0			49
 #define SM8650_MASTER_VIDEO			50
 #define SM8650_MASTER_VIDEO_CV_PROC		51
 #define SM8650_MASTER_VIDEO_PROC		52
 #define SM8650_MASTER_VIDEO_V_PROC		53
 #define SM8650_SLAVE_A1NOC_SNOC			54
 #define SM8650_SLAVE_A2NOC_SNOC			55
 #define SM8650_SLAVE_AHB2PHY_NORTH		56
 #define SM8650_SLAVE_AHB2PHY_SOUTH		57
 #define SM8650_SLAVE_ANOC_PCIE_GEM_NOC		58
 #define SM8650_SLAVE_AOSS			59
 #define SM8650_SLAVE_APPSS			60
 #define SM8650_SLAVE_CAMERA_CFG			61
 #define SM8650_SLAVE_CDSP_MEM_NOC		62
 #define SM8650_SLAVE_CLK_CTL			63
 #define SM8650_SLAVE_CNOC_CFG			64
 #define SM8650_SLAVE_CNOC_MNOC_CFG		65
 #define SM8650_SLAVE_CNOC_MSS			66
 #define SM8650_SLAVE_CPR_HMX			67
 #define SM8650_SLAVE_CPR_NSPCX			68
 #define SM8650_SLAVE_CRYPTO_0_CFG		69
 #define SM8650_SLAVE_CX_RDPM			70
 #define SM8650_SLAVE_DDRSS_CFG			71
 #define SM8650_SLAVE_DISPLAY_CFG		72
 #define SM8650_SLAVE_EBI1			73
 #define SM8650_SLAVE_GEM_NOC_CNOC		74
 #define SM8650_SLAVE_GFX3D_CFG			75
 #define SM8650_SLAVE_I2C			76
 #define SM8650_SLAVE_I3C_IBI0_CFG		77
 #define SM8650_SLAVE_I3C_IBI1_CFG		78
 #define SM8650_SLAVE_IMEM			79
 #define SM8650_SLAVE_IMEM_CFG			80
 #define SM8650_SLAVE_IPA_CFG			81
 #define SM8650_SLAVE_IPC_ROUTER_CFG		82
 #define SM8650_SLAVE_LLCC			83
 #define SM8650_SLAVE_LPASS_GEM_NOC		84
 #define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC	85
 #define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC	86
 #define SM8650_SLAVE_MEM_NOC_PCIE_SNOC		87
 #define SM8650_SLAVE_MNOC_HF_MEM_NOC		88
 #define SM8650_SLAVE_MNOC_SF_MEM_NOC		89
 #define SM8650_SLAVE_MX_2_RDPM			90
 #define SM8650_SLAVE_MX_RDPM			91
 #define SM8650_SLAVE_NSP_QTB_CFG		92
 #define SM8650_SLAVE_PCIE_0			93
 #define SM8650_SLAVE_PCIE_1			94
 #define SM8650_SLAVE_PCIE_0_CFG			95
 #define SM8650_SLAVE_PCIE_1_CFG			96
 #define SM8650_SLAVE_PCIE_ANOC_CFG		97
 #define SM8650_SLAVE_PCIE_RSCC			98
 #define SM8650_SLAVE_PDM			99
 #define SM8650_SLAVE_PRNG			100
 #define SM8650_SLAVE_QDSS_CFG			101
 #define SM8650_SLAVE_QDSS_STM			102
 #define SM8650_SLAVE_QSPI_0			103
 #define SM8650_SLAVE_QUP_1			104
 #define SM8650_SLAVE_QUP_2			105
 #define SM8650_SLAVE_QUP_3			106
 #define SM8650_SLAVE_QUP_CORE_0			107
 #define SM8650_SLAVE_QUP_CORE_1			108
 #define SM8650_SLAVE_QUP_CORE_2			109
 #define SM8650_SLAVE_RBCPR_CX_CFG		110
 #define SM8650_SLAVE_RBCPR_MMCX_CFG		111
 #define SM8650_SLAVE_RBCPR_MXA_CFG		112
 #define SM8650_SLAVE_RBCPR_MXC_CFG		113
 #define SM8650_SLAVE_SDCC_2			114
 #define SM8650_SLAVE_SDCC_4			115
 #define SM8650_SLAVE_SERVICE_CNOC		116
 #define SM8650_SLAVE_SERVICE_CNOC_CFG		117
 #define SM8650_SLAVE_SERVICE_MNOC		118
 #define SM8650_SLAVE_SERVICE_PCIE_ANOC		119
 #define SM8650_SLAVE_SNOC_GEM_NOC_SF		120
 #define SM8650_SLAVE_SPSS_CFG			121
 #define SM8650_SLAVE_TCSR			122
 #define SM8650_SLAVE_TCU			123
 #define SM8650_SLAVE_TLMM			124
 #define SM8650_SLAVE_TME_CFG			125
 #define SM8650_SLAVE_UFS_MEM_CFG		126
 #define SM8650_SLAVE_USB3_0			127
 #define SM8650_SLAVE_VENUS_CFG			128
 #define SM8650_SLAVE_VSENSE_CTRL_CFG		129

 #endif
	/* SPDX-License-Identifier: GPL-2.0-only */
	/*
	* SM8650 interconnect IDs
	*
	* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
	* Copyright (c) 2023, Linaro Limited
	*/

	#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8650_H
	#define __DRIVERS_INTERCONNECT_QCOM_SM8650_H

	#define SM8650_MASTER_A1NOC_SNOC 0
	#define SM8650_MASTER_A2NOC_SNOC 1
	#define SM8650_MASTER_ANOC_PCIE_GEM_NOC 2
	#define SM8650_MASTER_APPSS_PROC 3
	#define SM8650_MASTER_CAMNOC_HF 4
	#define SM8650_MASTER_CAMNOC_ICP 5
	#define SM8650_MASTER_CAMNOC_SF 6
	#define SM8650_MASTER_CDSP_HCP 7
	#define SM8650_MASTER_CDSP_PROC 8
	#define SM8650_MASTER_CNOC_CFG 9
	#define SM8650_MASTER_CNOC_MNOC_CFG 10
	#define SM8650_MASTER_COMPUTE_NOC 11
	#define SM8650_MASTER_CRYPTO 12
	#define SM8650_MASTER_GEM_NOC_CNOC 13
	#define SM8650_MASTER_GEM_NOC_PCIE_SNOC 14
	#define SM8650_MASTER_GFX3D 15
	#define SM8650_MASTER_GIC 16
	#define SM8650_MASTER_GPU_TCU 17
	#define SM8650_MASTER_IPA 18
	#define SM8650_MASTER_LLCC 19
	#define SM8650_MASTER_LPASS_GEM_NOC 20
	#define SM8650_MASTER_LPASS_LPINOC 21
	#define SM8650_MASTER_LPASS_PROC 22
	#define SM8650_MASTER_LPIAON_NOC 23
	#define SM8650_MASTER_MDP 24
	#define SM8650_MASTER_MNOC_HF_MEM_NOC 25
	#define SM8650_MASTER_MNOC_SF_MEM_NOC 26
	#define SM8650_MASTER_MSS_PROC 27
	#define SM8650_MASTER_PCIE_0 28
	#define SM8650_MASTER_PCIE_1 29
	#define SM8650_MASTER_PCIE_ANOC_CFG 30
	#define SM8650_MASTER_QDSS_BAM 31
	#define SM8650_MASTER_QDSS_ETR 32
	#define SM8650_MASTER_QDSS_ETR_1 33
	#define SM8650_MASTER_QSPI_0 34
	#define SM8650_MASTER_QUP_1 35
	#define SM8650_MASTER_QUP_2 36
	#define SM8650_MASTER_QUP_3 37
	#define SM8650_MASTER_QUP_CORE_0 38
	#define SM8650_MASTER_QUP_CORE_1 39
	#define SM8650_MASTER_QUP_CORE_2 40
	#define SM8650_MASTER_SDCC_2 41
	#define SM8650_MASTER_SDCC_4 42
	#define SM8650_MASTER_SNOC_SF_MEM_NOC 43
	#define SM8650_MASTER_SP 44
	#define SM8650_MASTER_SYS_TCU 45
	#define SM8650_MASTER_UBWC_P 46
	#define SM8650_MASTER_UBWC_P_TCU 47
	#define SM8650_MASTER_UFS_MEM 48
	#define SM8650_MASTER_USB3_0 49
	#define SM8650_MASTER_VIDEO 50
	#define SM8650_MASTER_VIDEO_CV_PROC 51
	#define SM8650_MASTER_VIDEO_PROC 52
	#define SM8650_MASTER_VIDEO_V_PROC 53
	#define SM8650_SLAVE_A1NOC_SNOC 54
	#define SM8650_SLAVE_A2NOC_SNOC 55
	#define SM8650_SLAVE_AHB2PHY_NORTH 56
	#define SM8650_SLAVE_AHB2PHY_SOUTH 57
	#define SM8650_SLAVE_ANOC_PCIE_GEM_NOC 58
	#define SM8650_SLAVE_AOSS 59
	#define SM8650_SLAVE_APPSS 60
	#define SM8650_SLAVE_CAMERA_CFG 61
	#define SM8650_SLAVE_CDSP_MEM_NOC 62
	#define SM8650_SLAVE_CLK_CTL 63
	#define SM8650_SLAVE_CNOC_CFG 64
	#define SM8650_SLAVE_CNOC_MNOC_CFG 65
	#define SM8650_SLAVE_CNOC_MSS 66
	#define SM8650_SLAVE_CPR_HMX 67
	#define SM8650_SLAVE_CPR_NSPCX 68
	#define SM8650_SLAVE_CRYPTO_0_CFG 69
	#define SM8650_SLAVE_CX_RDPM 70
	#define SM8650_SLAVE_DDRSS_CFG 71
	#define SM8650_SLAVE_DISPLAY_CFG 72
	#define SM8650_SLAVE_EBI1 73
	#define SM8650_SLAVE_GEM_NOC_CNOC 74
	#define SM8650_SLAVE_GFX3D_CFG 75
	#define SM8650_SLAVE_I2C 76
	#define SM8650_SLAVE_I3C_IBI0_CFG 77
	#define SM8650_SLAVE_I3C_IBI1_CFG 78
	#define SM8650_SLAVE_IMEM 79
	#define SM8650_SLAVE_IMEM_CFG 80
	#define SM8650_SLAVE_IPA_CFG 81
	#define SM8650_SLAVE_IPC_ROUTER_CFG 82
	#define SM8650_SLAVE_LLCC 83
	#define SM8650_SLAVE_LPASS_GEM_NOC 84
	#define SM8650_SLAVE_LPIAON_NOC_LPASS_AG_NOC 85
	#define SM8650_SLAVE_LPICX_NOC_LPIAON_NOC 86
	#define SM8650_SLAVE_MEM_NOC_PCIE_SNOC 87
	#define SM8650_SLAVE_MNOC_HF_MEM_NOC 88
	#define SM8650_SLAVE_MNOC_SF_MEM_NOC 89
	#define SM8650_SLAVE_MX_2_RDPM 90
	#define SM8650_SLAVE_MX_RDPM 91
	#define SM8650_SLAVE_NSP_QTB_CFG 92
	#define SM8650_SLAVE_PCIE_0 93
	#define SM8650_SLAVE_PCIE_1 94
	#define SM8650_SLAVE_PCIE_0_CFG 95
	#define SM8650_SLAVE_PCIE_1_CFG 96
	#define SM8650_SLAVE_PCIE_ANOC_CFG 97
	#define SM8650_SLAVE_PCIE_RSCC 98
	#define SM8650_SLAVE_PDM 99
	#define SM8650_SLAVE_PRNG 100
	#define SM8650_SLAVE_QDSS_CFG 101
	#define SM8650_SLAVE_QDSS_STM 102
	#define SM8650_SLAVE_QSPI_0 103
	#define SM8650_SLAVE_QUP_1 104
	#define SM8650_SLAVE_QUP_2 105
	#define SM8650_SLAVE_QUP_3 106
	#define SM8650_SLAVE_QUP_CORE_0 107
	#define SM8650_SLAVE_QUP_CORE_1 108
	#define SM8650_SLAVE_QUP_CORE_2 109
	#define SM8650_SLAVE_RBCPR_CX_CFG 110
	#define SM8650_SLAVE_RBCPR_MMCX_CFG 111
	#define SM8650_SLAVE_RBCPR_MXA_CFG 112
	#define SM8650_SLAVE_RBCPR_MXC_CFG 113
	#define SM8650_SLAVE_SDCC_2 114
	#define SM8650_SLAVE_SDCC_4 115
	#define SM8650_SLAVE_SERVICE_CNOC 116
	#define SM8650_SLAVE_SERVICE_CNOC_CFG 117
	#define SM8650_SLAVE_SERVICE_MNOC 118
	#define SM8650_SLAVE_SERVICE_PCIE_ANOC 119
	#define SM8650_SLAVE_SNOC_GEM_NOC_SF 120
	#define SM8650_SLAVE_SPSS_CFG 121
	#define SM8650_SLAVE_TCSR 122
	#define SM8650_SLAVE_TCU 123
	#define SM8650_SLAVE_TLMM 124
	#define SM8650_SLAVE_TME_CFG 125
	#define SM8650_SLAVE_UFS_MEM_CFG 126
	#define SM8650_SLAVE_USB3_0 127
	#define SM8650_SLAVE_VENUS_CFG 128
	#define SM8650_SLAVE_VSENSE_CTRL_CFG 129

	#endif