| [ |
| { |
| "MetricName": "branch_miss_pred_rate", |
| "MetricExpr": "BR_MIS_PRED / BR_PRED", |
| "BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch", |
| "MetricGroup": "branch", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "bus_utilization", |
| "MetricExpr": "BUS_ACCESS / (BUS_CYCLES * 1)", |
| "BriefDescription": "Core-to-uncore bus utilization", |
| "MetricGroup": "Bus", |
| "ScaleUnit": "100percent of bus cycles" |
| }, |
| { |
| "MetricName": "l1d_cache_miss_ratio", |
| "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE", |
| "BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.", |
| "MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness", |
| "ScaleUnit": "1per cache access" |
| }, |
| { |
| "MetricName": "l1i_cache_miss_ratio", |
| "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE", |
| "BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.", |
| "MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness", |
| "ScaleUnit": "1per cache access" |
| }, |
| { |
| "MetricName": "Miss_Ratio;l1d_cache_read_miss", |
| "MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD", |
| "BriefDescription": "L1D cache read miss rate", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "1per cache read access" |
| }, |
| { |
| "MetricName": "l2_cache_miss_ratio", |
| "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE", |
| "BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.", |
| "MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness", |
| "ScaleUnit": "1per cache access" |
| }, |
| { |
| "MetricName": "l1i_cache_read_miss_rate", |
| "MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE", |
| "BriefDescription": "L1I cache read miss rate", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "1per cache access" |
| }, |
| { |
| "MetricName": "l2d_cache_read_miss_rate", |
| "MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD", |
| "BriefDescription": "L2 cache read miss rate", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "1per cache read access" |
| }, |
| { |
| "MetricName": "l1d_cache_miss_mpki", |
| "MetricExpr": "(L1D_CACHE_LMISS_RD * 1e3) / INST_RETIRED", |
| "BriefDescription": "Misses per thousand instructions (data)", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "1MPKI" |
| }, |
| { |
| "MetricName": "l1i_cache_miss_mpki", |
| "MetricExpr": "(L1I_CACHE_LMISS * 1e3) / INST_RETIRED", |
| "BriefDescription": "Misses per thousand instructions (instruction)", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "1MPKI" |
| }, |
| { |
| "MetricName": "simd_percentage", |
| "MetricExpr": "ASE_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "crypto_percentage", |
| "MetricExpr": "CRYPTO_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "gflops", |
| "MetricExpr": "VFP_SPEC / (duration_time * 1e9)", |
| "BriefDescription": "Giga-floating point operations per second", |
| "MetricGroup": "InstructionMix" |
| }, |
| { |
| "MetricName": "integer_dp_percentage", |
| "MetricExpr": "DP_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "ipc", |
| "MetricExpr": "INST_RETIRED / CPU_CYCLES", |
| "BriefDescription": "This metric measures the number of instructions retired per cycle.", |
| "MetricGroup": "General", |
| "ScaleUnit": "1per cycle" |
| }, |
| { |
| "MetricName": "load_percentage", |
| "MetricExpr": "LD_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "load_store_spec_rate", |
| "MetricExpr": "LDST_SPEC / INST_SPEC", |
| "BriefDescription": "The rate of load or store instructions speculatively executed to overall instructions speclatively executed", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "retired_mips", |
| "MetricExpr": "INST_RETIRED / (duration_time * 1e6)", |
| "BriefDescription": "Millions of instructions per second", |
| "MetricGroup": "InstructionMix" |
| }, |
| { |
| "MetricName": "spec_utilization_mips", |
| "MetricExpr": "INST_SPEC / (duration_time * 1e6)", |
| "BriefDescription": "Millions of instructions per second", |
| "MetricGroup": "PEutilization" |
| }, |
| { |
| "MetricName": "pc_write_spec_rate", |
| "MetricExpr": "PC_WRITE_SPEC / INST_SPEC", |
| "BriefDescription": "The rate of software change of the PC speculatively executed to overall instructions speclatively executed", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "store_percentage", |
| "MetricExpr": "ST_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "scalar_fp_percentage", |
| "MetricExpr": "VFP_SPEC / INST_SPEC", |
| "BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.", |
| "MetricGroup": "Operation_Mix", |
| "ScaleUnit": "100percent of operations" |
| }, |
| { |
| "MetricName": "retired_rate", |
| "MetricExpr": "OP_RETIRED / OP_SPEC", |
| "BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)", |
| "MetricGroup": "General", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "wasted", |
| "MetricExpr": "1 - (OP_RETIRED / (CPU_CYCLES * #slots))", |
| "BriefDescription": "Of all the micro-operations issued, what proportion are lost", |
| "MetricGroup": "General", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "wasted_rate", |
| "MetricExpr": "1 - OP_RETIRED / OP_SPEC", |
| "BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)", |
| "MetricGroup": "General", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "stall_backend_cache_rate", |
| "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", |
| "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss", |
| "MetricGroup": "Stall", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_backend_resource_rate", |
| "MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES", |
| "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full", |
| "MetricGroup": "Stall", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_backend_tlb_rate", |
| "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", |
| "BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss", |
| "MetricGroup": "Stall", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_frontend_cache_rate", |
| "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", |
| "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss", |
| "MetricGroup": "Stall", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_frontend_tlb_rate", |
| "MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES", |
| "BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss", |
| "MetricGroup": "Stall", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "dtlb_walk_ratio", |
| "MetricExpr": "DTLB_WALK / L1D_TLB", |
| "BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.", |
| "MetricGroup": "Miss_Ratio;DTLB_Effectiveness", |
| "ScaleUnit": "1per TLB access" |
| }, |
| { |
| "MetricName": "itlb_walk_ratio", |
| "MetricExpr": "ITLB_WALK / L1I_TLB", |
| "BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.", |
| "MetricGroup": "Miss_Ratio;ITLB_Effectiveness", |
| "ScaleUnit": "1per TLB access" |
| }, |
| { |
| "ArchStdEvent": "backend_bound" |
| }, |
| { |
| "ArchStdEvent": "frontend_bound", |
| "MetricExpr": "100 - (retired_fraction + slots_lost_misspeculation_fraction + backend_bound)" |
| }, |
| { |
| "MetricName": "slots_lost_misspeculation_fraction", |
| "MetricExpr": "(OP_SPEC - OP_RETIRED) / (CPU_CYCLES * #slots)", |
| "BriefDescription": "Fraction of slots lost due to misspeculation", |
| "DefaultMetricgroupName": "TopdownL1", |
| "MetricGroup": "Default;TopdownL1", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "retired_fraction", |
| "MetricExpr": "OP_RETIRED / (CPU_CYCLES * #slots)", |
| "BriefDescription": "Fraction of slots retiring, useful work", |
| "DefaultMetricgroupName": "TopdownL1", |
| "MetricGroup": "Default;TopdownL1", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "backend_core", |
| "MetricExpr": "(backend_bound / 100) - backend_memory", |
| "BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "backend_memory", |
| "MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE) / CPU_CYCLES", |
| "BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "100%" |
| }, |
| { |
| "MetricName": "branch_mispredict", |
| "MetricExpr": "(BR_MIS_PRED_RETIRED / GPC_FLUSH) * slots_lost_misspeculation_fraction", |
| "BriefDescription": "Fraction of slots lost due to branch misprediciton", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "1percent of slots" |
| }, |
| { |
| "MetricName": "frontend_bandwidth", |
| "MetricExpr": "frontend_bound - frontend_latency", |
| "BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "1percent of slots" |
| }, |
| { |
| "MetricName": "frontend_latency", |
| "MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - ((frontend_bound / 100) * CPU_CYCLES * #slots)) / #slots)) / CPU_CYCLES", |
| "BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "other_miss_pred", |
| "MetricExpr": "slots_lost_misspeculation_fraction - branch_mispredict", |
| "BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "1percent of slots" |
| }, |
| { |
| "MetricName": "pipe_utilization", |
| "MetricExpr": "100 * ((IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6))", |
| "BriefDescription": "Fraction of execute slots utilized", |
| "MetricGroup": "TopdownL2", |
| "ScaleUnit": "1percent of slots" |
| }, |
| { |
| "MetricName": "d_cache_l2_miss_rate", |
| "MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "d_cache_miss_rate", |
| "MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "d_tlb_miss_rate", |
| "MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "fsu_pipe_utilization", |
| "MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)", |
| "BriefDescription": "Fraction of FSU execute slots utilized", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "i_cache_miss_rate", |
| "MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "i_tlb_miss_rate", |
| "MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "ixu_pipe_utilization", |
| "MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES * #slots)", |
| "BriefDescription": "Fraction of IXU execute slots utilized", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "stall_recovery_rate", |
| "MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery", |
| "MetricGroup": "TopdownL3", |
| "ScaleUnit": "100percent of slots" |
| }, |
| { |
| "MetricName": "stall_fsu_sched_rate", |
| "MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full", |
| "MetricGroup": "TopdownL4", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_ixu_sched_rate", |
| "MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full", |
| "MetricGroup": "TopdownL4", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_lob_id_rate", |
| "MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full", |
| "MetricGroup": "TopdownL4", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_rob_id_rate", |
| "MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full", |
| "MetricGroup": "TopdownL4", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "stall_sob_id_rate", |
| "MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES", |
| "BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full", |
| "MetricGroup": "TopdownL4", |
| "ScaleUnit": "100percent of cycles" |
| }, |
| { |
| "MetricName": "l1d_cache_access_demand", |
| "MetricExpr": "L1D_CACHE_RW / L1D_CACHE", |
| "BriefDescription": "L1D cache access - demand", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "l1d_cache_access_prefetces", |
| "MetricExpr": "L1D_CACHE_PRFM / L1D_CACHE", |
| "BriefDescription": "L1D cache access - prefetch", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "l1d_cache_demand_misses", |
| "MetricExpr": "L1D_CACHE_REFILL_RW / L1D_CACHE", |
| "BriefDescription": "L1D cache demand misses", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "l1d_cache_demand_misses_read", |
| "MetricExpr": "L1D_CACHE_REFILL_RD / L1D_CACHE", |
| "BriefDescription": "L1D cache demand misses - read", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "l1d_cache_demand_misses_write", |
| "MetricExpr": "L1D_CACHE_REFILL_WR / L1D_CACHE", |
| "BriefDescription": "L1D cache demand misses - write", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "l1d_cache_prefetch_misses", |
| "MetricExpr": "L1D_CACHE_REFILL_PRFM / L1D_CACHE", |
| "BriefDescription": "L1D cache prefetch misses", |
| "MetricGroup": "Cache", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "ase_scalar_mix", |
| "MetricExpr": "ASE_SCALAR_SPEC / OP_SPEC", |
| "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) scalar operations", |
| "MetricGroup": "Instructions", |
| "ScaleUnit": "100percent of cache acceses" |
| }, |
| { |
| "MetricName": "ase_vector_mix", |
| "MetricExpr": "ASE_VECTOR_SPEC / OP_SPEC", |
| "BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) vector operations", |
| "MetricGroup": "Instructions", |
| "ScaleUnit": "100percent of cache acceses" |
| } |
| ] |
