| [ |
| { |
| "BriefDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels).", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", |
| "UMask": "0x20", |
| "Unit": "imc_free_running_0" |
| }, |
| { |
| "BriefDescription": "Counts every read and write request entering the Memory Controller 0.", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.", |
| "UMask": "0x10", |
| "Unit": "imc_free_running_0" |
| }, |
| { |
| "BriefDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels).", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", |
| "UMask": "0x30", |
| "Unit": "imc_free_running_0" |
| }, |
| { |
| "BriefDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels).", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", |
| "UMask": "0x20", |
| "Unit": "imc_free_running_1" |
| }, |
| { |
| "BriefDescription": "Counts every read and write request entering the Memory Controller 1.", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW.", |
| "UMask": "0x10", |
| "Unit": "imc_free_running_1" |
| }, |
| { |
| "BriefDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels).", |
| "EventCode": "0xff", |
| "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", |
| "PerPkg": "1", |
| "PublicDescription": "Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data.", |
| "UMask": "0x30", |
| "Unit": "imc_free_running_1" |
| }, |
| { |
| "BriefDescription": "ACT command for a read request sent to DRAM", |
| "EventCode": "0x24", |
| "EventName": "UNC_M_ACT_COUNT_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "ACT command sent to DRAM", |
| "EventCode": "0x26", |
| "EventName": "UNC_M_ACT_COUNT_TOTAL", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "ACT command for a write request sent to DRAM", |
| "EventCode": "0x25", |
| "EventName": "UNC_M_ACT_COUNT_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Read CAS command sent to DRAM", |
| "EventCode": "0x22", |
| "EventName": "UNC_M_CAS_COUNT_RD", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Write CAS command sent to DRAM", |
| "EventCode": "0x23", |
| "EventName": "UNC_M_CAS_COUNT_WR", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", |
| "EventCode": "0x28", |
| "EventName": "UNC_M_PRE_COUNT_IDLE", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "PRE command sent to DRAM for a read/write request", |
| "EventCode": "0x27", |
| "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data.", |
| "EventCode": "0x3A", |
| "EventName": "UNC_M_RD_DATA", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data.", |
| "EventCode": "0x3C", |
| "EventName": "UNC_M_TOTAL_DATA", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| }, |
| { |
| "BriefDescription": "Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data.", |
| "EventCode": "0x3B", |
| "EventName": "UNC_M_WR_DATA", |
| "PerPkg": "1", |
| "Unit": "iMC" |
| } |
| ] |