Documentation/devicetree/bindings/net/adi,adin.yaml

# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/adi,adin.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices ADIN1200/ADIN1300 PHY

maintainers:
  - Alexandru Tachici <alexandru.tachici@analog.com>

description: |
  Bindings for Analog Devices Industrial Ethernet PHYs

allOf:
  - $ref: ethernet-phy.yaml#

properties:
  adi,rx-internal-delay-ps:
    description: |
      RGMII RX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
    enum: [ 1600, 1800, 2000, 2200, 2400 ]
    default: 2000

  adi,tx-internal-delay-ps:
    description: |
      RGMII TX Clock Delay used only when PHY operates in RGMII mode with
      internal delay (phy-mode is 'rgmii-id' or 'rgmii-txid') in pico-seconds.
    enum: [ 1600, 1800, 2000, 2200, 2400 ]
    default: 2000

  adi,fifo-depth-bits:
    description: |
      When operating in RMII mode, this option configures the FIFO depth.
    enum: [ 4, 8, 12, 16, 20, 24 ]
    default: 8

  adi,phy-output-clock:
    description: |
      Select clock output on GP_CLK pin. Two clocks are available:
      A 25MHz reference and a free-running 125MHz.
      The phy can alternatively automatically switch between the reference and
      the 125MHz clocks based on its internal state.
    $ref: /schemas/types.yaml#/definitions/string
    enum:
      - 25mhz-reference
      - 125mhz-free-running
      - adaptive-free-running

  adi,phy-output-reference-clock:
    description: Enable 25MHz reference clock output on CLK25_REF pin.
    type: boolean

unevaluatedProperties: false

examples:
  - |
    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rgmii-id";

        ethernet-phy@0 {
            reg = <0>;

            adi,rx-internal-delay-ps = <1800>;
            adi,tx-internal-delay-ps = <2200>;
        };
    };
  - |
    ethernet {
        #address-cells = <1>;
        #size-cells = <0>;

        phy-mode = "rmii";

        ethernet-phy@1 {
            reg = <1>;

            adi,fifo-depth-bits = <16>;
        };
    };