arch/arm/boot/dts/armada-xp.dtsi

/*
 * Device Tree Include file for Marvell Armada XP family SoC
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 * Ben Dooks <ben.dooks@codethink.co.uk>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * Contains definitions specific to the Armada XP SoC that are not
 * common to all Armada SoCs.
 */

/include/ "armada-370-xp.dtsi"

/ {
	model = "Marvell Armada XP family SoC";
	compatible = "marvell,armadaxp", "marvell,armada-370-xp";


	soc {
		L2: l2-cache {
			compatible = "marvell,aurora-system-cache";
			reg = <0x08000 0x1000>;
			cache-id-part = <0x100>;
			wt-override;
		};

		mpic: interrupt-controller@20000 {
		      reg = <0x20a00 0x2d0>,
			    <0x21070 0x58>;
		};

		armada-370-xp-pmsu@22000 {
			compatible = "marvell,armada-370-xp-pmsu";
			reg = <0x22100 0x430>,
			      <0x20800 0x20>;
		};

		serial@12200 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12200 0x100>;
				reg-shift = <2>;
				interrupts = <43>;
				reg-io-width = <1>;
				status = "disabled";
		};
		serial@12300 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12300 0x100>;
				reg-shift = <2>;
				interrupts = <44>;
				reg-io-width = <1>;
				status = "disabled";
		};

		timer@20300 {
				marvell,timer-25Mhz;
		};

		coreclk: mvebu-sar@18230 {
			compatible = "marvell,armada-xp-core-clock";
			reg = <0x18230 0x08>;
			#clock-cells = <1>;
		};

		cpuclk: clock-complex@18700 {
			#clock-cells = <1>;
			compatible = "marvell,armada-xp-cpu-clock";
			reg = <0x18700 0xA0>;
			clocks = <&coreclk 1>;
		};

		gateclk: clock-gating-control@18220 {
			compatible = "marvell,armada-xp-gating-clock";
			reg = <0x18220 0x4>;
			clocks = <&coreclk 0>;
			#clock-cells = <1>;
		};

		system-controller@18200 {
				compatible = "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x500>;
		};

		ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x2500>;
				interrupts = <12>;
				clocks = <&gateclk 2>;
				status = "disabled";
		};

		xor@60900 {
			compatible = "marvell,orion-xor";
			reg = <0x60900 0x100
			       0x60b00 0x100>;
			clocks = <&gateclk 22>;
			status = "okay";

			xor10 {
				interrupts = <51>;
				dmacap,memcpy;
				dmacap,xor;
			};
			xor11 {
				interrupts = <52>;
				dmacap,memcpy;
				dmacap,xor;
				dmacap,memset;
			};
		};

		xor@f0900 {
			compatible = "marvell,orion-xor";
			reg = <0xF0900 0x100
			       0xF0B00 0x100>;
			clocks = <&gateclk 28>;
			status = "okay";

			xor00 {
				interrupts = <94>;
				dmacap,memcpy;
				dmacap,xor;
			};
			xor01 {
				interrupts = <95>;
				dmacap,memcpy;
				dmacap,xor;
				dmacap,memset;
			};
		};

		usb@50000 {
			clocks = <&gateclk 18>;
		};

		usb@51000 {
			clocks = <&gateclk 19>;
		};

		usb@52000 {
			compatible = "marvell,orion-ehci";
			reg = <0x52000 0x500>;
			interrupts = <47>;
			clocks = <&gateclk 20>;
			status = "disabled";
		};

		thermal@182b0 {
			compatible = "marvell,armadaxp-thermal";
			reg = <0x182b0 0x4
			       0x184d0 0x4>;
			status = "okay";
		};
	};
};