| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/qcom,gcc-ipq8074.h> |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| model = "Qualcomm Technologies, Inc. IPQ8074"; |
| compatible = "qcom,ipq8074"; |
| interrupt-parent = <&intc>; |
| |
| clocks { |
| sleep_clk: sleep_clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <32768>; |
| #clock-cells = <0>; |
| }; |
| |
| xo: xo { |
| compatible = "fixed-clock"; |
| clock-frequency = <19200000>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <0x1>; |
| #size-cells = <0x0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| next-level-cache = <&L2_0>; |
| enable-method = "psci"; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x1>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x2>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| CPU3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| enable-method = "psci"; |
| reg = <0x3>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| smem@4ab00000 { |
| compatible = "qcom,smem"; |
| reg = <0x0 0x4ab00000 0x0 0x00100000>; |
| no-map; |
| |
| hwlocks = <&tcsr_mutex 0>; |
| }; |
| |
| memory@4ac00000 { |
| no-map; |
| reg = <0x0 0x4ac00000 0x0 0x00400000>; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-ipq8074", "qcom,scm"; |
| }; |
| }; |
| |
| soc: soc { |
| #address-cells = <0x1>; |
| #size-cells = <0x1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| ssphy_1: phy@58000 { |
| compatible = "qcom,ipq8074-qmp-usb3-phy"; |
| reg = <0x00058000 0x1c4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB1_AUX_CLK>, |
| <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, |
| <&xo>; |
| clock-names = "aux", "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_USB1_PHY_BCR>, |
| <&gcc GCC_USB3PHY_1_PHY_BCR>; |
| reset-names = "phy","common"; |
| status = "disabled"; |
| |
| usb1_ssphy: phy@58200 { |
| reg = <0x00058200 0x130>, /* Tx */ |
| <0x00058400 0x200>, /* Rx */ |
| <0x00058800 0x1f8>, /* PCS */ |
| <0x00058600 0x044>; /* PCS misc */ |
| #phy-cells = <0>; |
| #clock-cells = <0>; |
| clocks = <&gcc GCC_USB1_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3phy_1_cc_pipe_clk"; |
| }; |
| }; |
| |
| qusb_phy_1: phy@59000 { |
| compatible = "qcom,ipq8074-qusb2-phy"; |
| reg = <0x00059000 0x180>; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, |
| <&xo>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_QUSB2_1_PHY_BCR>; |
| status = "disabled"; |
| }; |
| |
| ssphy_0: phy@78000 { |
| compatible = "qcom,ipq8074-qmp-usb3-phy"; |
| reg = <0x00078000 0x1c4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB0_AUX_CLK>, |
| <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
| <&xo>; |
| clock-names = "aux", "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_USB0_PHY_BCR>, |
| <&gcc GCC_USB3PHY_0_PHY_BCR>; |
| reset-names = "phy","common"; |
| status = "disabled"; |
| |
| usb0_ssphy: phy@78200 { |
| reg = <0x00078200 0x130>, /* Tx */ |
| <0x00078400 0x200>, /* Rx */ |
| <0x00078800 0x1f8>, /* PCS */ |
| <0x00078600 0x044>; /* PCS misc */ |
| #phy-cells = <0>; |
| #clock-cells = <0>; |
| clocks = <&gcc GCC_USB0_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3phy_0_cc_pipe_clk"; |
| }; |
| }; |
| |
| qusb_phy_0: phy@79000 { |
| compatible = "qcom,ipq8074-qusb2-phy"; |
| reg = <0x00079000 0x180>; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, |
| <&xo>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_QUSB2_0_PHY_BCR>; |
| status = "disabled"; |
| }; |
| |
| pcie_qmp0: phy@84000 { |
| compatible = "qcom,ipq8074-qmp-gen3-pcie-phy"; |
| reg = <0x00084000 0x1bc>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_PCIE0_AUX_CLK>, |
| <&gcc GCC_PCIE0_AHB_CLK>; |
| clock-names = "aux", "cfg_ahb"; |
| resets = <&gcc GCC_PCIE0_PHY_BCR>, |
| <&gcc GCC_PCIE0PHY_PHY_BCR>; |
| reset-names = "phy", |
| "common"; |
| status = "disabled"; |
| |
| pcie_phy0: phy@84200 { |
| reg = <0x84200 0x16c>, |
| <0x84400 0x200>, |
| <0x84800 0x1f0>, |
| <0x84c00 0xf4>; |
| #phy-cells = <0>; |
| #clock-cells = <0>; |
| clocks = <&gcc GCC_PCIE0_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "pcie20_phy0_pipe_clk"; |
| }; |
| }; |
| |
| pcie_qmp1: phy@8e000 { |
| compatible = "qcom,ipq8074-qmp-pcie-phy"; |
| reg = <0x0008e000 0x1c4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_PCIE1_AUX_CLK>, |
| <&gcc GCC_PCIE1_AHB_CLK>; |
| clock-names = "aux", "cfg_ahb"; |
| resets = <&gcc GCC_PCIE1_PHY_BCR>, |
| <&gcc GCC_PCIE1PHY_PHY_BCR>; |
| reset-names = "phy", |
| "common"; |
| status = "disabled"; |
| |
| pcie_phy1: phy@8e200 { |
| reg = <0x8e200 0x130>, |
| <0x8e400 0x200>, |
| <0x8e800 0x1f8>; |
| #phy-cells = <0>; |
| #clock-cells = <0>; |
| clocks = <&gcc GCC_PCIE1_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "pcie20_phy1_pipe_clk"; |
| }; |
| }; |
| |
| mdio: mdio@90000 { |
| compatible = "qcom,ipq8074-mdio", "qcom,ipq4019-mdio"; |
| reg = <0x00090000 0x64>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clocks = <&gcc GCC_MDIO_AHB_CLK>; |
| clock-names = "gcc_mdio_ahb_clk"; |
| |
| status = "disabled"; |
| }; |
| |
| qfprom: efuse@a4000 { |
| compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; |
| reg = <0x000a4000 0x2000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| prng: rng@e3000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0x000e3000 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| status = "disabled"; |
| }; |
| |
| tsens: thermal-sensor@4a9000 { |
| compatible = "qcom,ipq8074-tsens"; |
| reg = <0x4a9000 0x1000>, /* TM */ |
| <0x4a8000 0x1000>; /* SROT */ |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "combined"; |
| #qcom,sensors = <16>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| cryptobam: dma-controller@704000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x00704000 0x20000>; |
| interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_CRYPTO_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <1>; |
| qcom,controlled-remotely; |
| status = "disabled"; |
| }; |
| |
| crypto: crypto@73a000 { |
| compatible = "qcom,crypto-v5.1"; |
| reg = <0x0073a000 0x6000>; |
| clocks = <&gcc GCC_CRYPTO_AHB_CLK>, |
| <&gcc GCC_CRYPTO_AXI_CLK>, |
| <&gcc GCC_CRYPTO_CLK>; |
| clock-names = "iface", "bus", "core"; |
| dmas = <&cryptobam 2>, <&cryptobam 3>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| tlmm: pinctrl@1000000 { |
| compatible = "qcom,ipq8074-pinctrl"; |
| reg = <0x01000000 0x300000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| gpio-ranges = <&tlmm 0 0 70>; |
| #gpio-cells = <0x2>; |
| interrupt-controller; |
| #interrupt-cells = <0x2>; |
| |
| serial_4_pins: serial4-state { |
| pins = "gpio23", "gpio24"; |
| function = "blsp4_uart1"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| i2c_0_pins: i2c-0-state { |
| pins = "gpio42", "gpio43"; |
| function = "blsp1_i2c"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| spi_0_pins: spi-0-state { |
| pins = "gpio38", "gpio39", "gpio40", "gpio41"; |
| function = "blsp0_spi"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| hsuart_pins: hsuart-state { |
| pins = "gpio46", "gpio47", "gpio48", "gpio49"; |
| function = "blsp2_uart"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| |
| qpic_pins: qpic-state { |
| pins = "gpio1", "gpio3", "gpio4", |
| "gpio5", "gpio6", "gpio7", |
| "gpio8", "gpio10", "gpio11", |
| "gpio12", "gpio13", "gpio14", |
| "gpio15", "gpio16", "gpio17"; |
| function = "qpic"; |
| drive-strength = <8>; |
| bias-disable; |
| }; |
| }; |
| |
| gcc: gcc@1800000 { |
| compatible = "qcom,gcc-ipq8074"; |
| reg = <0x01800000 0x80000>; |
| clocks = <&xo>, <&sleep_clk>; |
| clock-names = "xo", "sleep_clk"; |
| #clock-cells = <1>; |
| #power-domain-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| tcsr_mutex: hwlock@1905000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x01905000 0x20000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| spmi_bus: spmi@200f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x0200f000 0x001000>, |
| <0x02400000 0x800000>, |
| <0x02c00000 0x800000>, |
| <0x03800000 0x200000>, |
| <0x0200a000 0x000700>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "periph_irq"; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| }; |
| |
| sdhc_1: mmc@7824900 { |
| compatible = "qcom,sdhci-msm-v4"; |
| reg = <0x7824900 0x500>, <0x7824000 0x800>; |
| reg-names = "hc", "core"; |
| |
| interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC1_AHB_CLK>, |
| <&gcc GCC_SDCC1_APPS_CLK>, |
| <&xo>; |
| clock-names = "iface", "core", "xo"; |
| resets = <&gcc GCC_SDCC1_BCR>; |
| max-frequency = <384000000>; |
| mmc-ddr-1_8v; |
| mmc-hs200-1_8v; |
| mmc-hs400-1_8v; |
| bus-width = <8>; |
| |
| status = "disabled"; |
| }; |
| |
| blsp_dma: dma-controller@7884000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x07884000 0x2b000>; |
| interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| blsp1_uart1: serial@78af000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078af000 0x200>; |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| |
| blsp1_uart3: serial@78b1000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078b1000 0x200>; |
| interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 4>, |
| <&blsp_dma 5>; |
| dma-names = "tx", "rx"; |
| pinctrl-0 = <&hsuart_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| blsp1_uart5: serial@78b3000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0x078b3000 0x200>; |
| interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| pinctrl-0 = <&serial_4_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| blsp1_spi1: spi@78b5000 { |
| compatible = "qcom,spi-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x078b5000 0x600>; |
| interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; |
| spi-max-frequency = <50000000>; |
| clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| dmas = <&blsp_dma 12>, <&blsp_dma 13>; |
| dma-names = "tx", "rx"; |
| pinctrl-0 = <&spi_0_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c2: i2c@78b6000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x078b6000 0x600>; |
| interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| dmas = <&blsp_dma 14>, <&blsp_dma 15>; |
| dma-names = "tx", "rx"; |
| pinctrl-0 = <&i2c_0_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c3: i2c@78b7000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x078b7000 0x600>; |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <100000>; |
| dmas = <&blsp_dma 16>, <&blsp_dma 17>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c5: i2c@78b9000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x78b9000 0x600>; |
| interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <400000>; |
| dmas = <&blsp_dma 20>, <&blsp_dma 21>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| blsp1_i2c6: i2c@78ba000 { |
| compatible = "qcom,i2c-qup-v2.2.1"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x078ba000 0x600>; |
| interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, |
| <&gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| clock-frequency = <100000>; |
| dmas = <&blsp_dma 22>, <&blsp_dma 23>; |
| dma-names = "tx", "rx"; |
| status = "disabled"; |
| }; |
| |
| qpic_bam: dma-controller@7984000 { |
| compatible = "qcom,bam-v1.7.0"; |
| reg = <0x07984000 0x1a000>; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_QPIC_AHB_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| status = "disabled"; |
| }; |
| |
| qpic_nand: nand-controller@79b0000 { |
| compatible = "qcom,ipq8074-nand"; |
| reg = <0x079b0000 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QPIC_CLK>, |
| <&gcc GCC_QPIC_AHB_CLK>; |
| clock-names = "core", "aon"; |
| |
| dmas = <&qpic_bam 0>, |
| <&qpic_bam 1>, |
| <&qpic_bam 2>; |
| dma-names = "tx", "rx", "cmd"; |
| pinctrl-0 = <&qpic_pins>; |
| pinctrl-names = "default"; |
| status = "disabled"; |
| }; |
| |
| usb_0: usb@8af8800 { |
| compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; |
| reg = <0x08af8800 0x400>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| <&gcc GCC_USB0_MASTER_CLK>, |
| <&gcc GCC_USB0_SLEEP_CLK>, |
| <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| clock-names = "cfg_noc", |
| "core", |
| "sleep", |
| "mock_utmi"; |
| |
| assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, |
| <&gcc GCC_USB0_MASTER_CLK>, |
| <&gcc GCC_USB0_MOCK_UTMI_CLK>; |
| assigned-clock-rates = <133330000>, |
| <133330000>, |
| <19200000>; |
| |
| power-domains = <&gcc USB0_GDSC>; |
| |
| resets = <&gcc GCC_USB0_BCR>; |
| status = "disabled"; |
| |
| dwc_0: usb@8a00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x8a00000 0xcd00>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&qusb_phy_0>, <&usb0_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| snps,is-utmi-l1-suspend; |
| snps,hird-threshold = /bits/ 8 <0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_u3_susphy_quirk; |
| dr_mode = "host"; |
| }; |
| }; |
| |
| usb_1: usb@8cf8800 { |
| compatible = "qcom,ipq8074-dwc3", "qcom,dwc3"; |
| reg = <0x08cf8800 0x400>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, |
| <&gcc GCC_USB1_MASTER_CLK>, |
| <&gcc GCC_USB1_SLEEP_CLK>, |
| <&gcc GCC_USB1_MOCK_UTMI_CLK>; |
| clock-names = "cfg_noc", |
| "core", |
| "sleep", |
| "mock_utmi"; |
| |
| assigned-clocks = <&gcc GCC_SYS_NOC_USB1_AXI_CLK>, |
| <&gcc GCC_USB1_MASTER_CLK>, |
| <&gcc GCC_USB1_MOCK_UTMI_CLK>; |
| assigned-clock-rates = <133330000>, |
| <133330000>, |
| <19200000>; |
| |
| power-domains = <&gcc USB1_GDSC>; |
| |
| resets = <&gcc GCC_USB1_BCR>; |
| status = "disabled"; |
| |
| dwc_1: usb@8c00000 { |
| compatible = "snps,dwc3"; |
| reg = <0x8c00000 0xcd00>; |
| interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&qusb_phy_1>, <&usb1_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| snps,is-utmi-l1-suspend; |
| snps,hird-threshold = /bits/ 8 <0x0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_u3_susphy_quirk; |
| dr_mode = "host"; |
| }; |
| }; |
| |
| intc: interrupt-controller@b000000 { |
| compatible = "qcom,msm-qgic2"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| #interrupt-cells = <0x3>; |
| reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; |
| ranges = <0 0xb00a000 0xffd>; |
| |
| v2m@0 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x0 0xffd>; |
| }; |
| }; |
| |
| watchdog: watchdog@b017000 { |
| compatible = "qcom,kpss-wdt"; |
| reg = <0xb017000 0x1000>; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| clocks = <&sleep_clk>; |
| timeout-sec = <30>; |
| }; |
| |
| apcs_glb: mailbox@b111000 { |
| compatible = "qcom,ipq8074-apcs-apps-global", |
| "qcom,ipq6018-apcs-apps-global"; |
| reg = <0x0b111000 0x1000>; |
| clocks = <&a53pll>, <&xo>; |
| clock-names = "pll", "xo"; |
| |
| #clock-cells = <1>; |
| #mbox-cells = <1>; |
| }; |
| |
| a53pll: clock@b116000 { |
| compatible = "qcom,ipq8074-a53pll"; |
| reg = <0x0b116000 0x40>; |
| #clock-cells = <0>; |
| clocks = <&xo>; |
| clock-names = "xo"; |
| }; |
| |
| timer@b120000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x0b120000 0x1000>; |
| |
| frame@b120000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b121000 0x1000>, |
| <0x0b122000 0x1000>; |
| }; |
| |
| frame@b123000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b123000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b124000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b124000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b125000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b125000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b126000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b126000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b127000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b127000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@b128000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x0b128000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| pcie1: pci@10000000 { |
| compatible = "qcom,pcie-ipq8074"; |
| reg = <0x10000000 0xf1d>, |
| <0x10000f20 0xa8>, |
| <0x00088000 0x2000>, |
| <0x10100000 0x1000>; |
| reg-names = "dbi", "elbi", "parf", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <1>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| max-link-speed = <2>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| phys = <&pcie_phy1>; |
| phy-names = "pciephy"; |
| |
| ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */ |
| <0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */ |
| |
| interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 142 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 143 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 144 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 145 |
| IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>, |
| <&gcc GCC_PCIE1_AXI_M_CLK>, |
| <&gcc GCC_PCIE1_AXI_S_CLK>, |
| <&gcc GCC_PCIE1_AHB_CLK>, |
| <&gcc GCC_PCIE1_AUX_CLK>; |
| clock-names = "iface", |
| "axi_m", |
| "axi_s", |
| "ahb", |
| "aux"; |
| resets = <&gcc GCC_PCIE1_PIPE_ARES>, |
| <&gcc GCC_PCIE1_SLEEP_ARES>, |
| <&gcc GCC_PCIE1_CORE_STICKY_ARES>, |
| <&gcc GCC_PCIE1_AXI_MASTER_ARES>, |
| <&gcc GCC_PCIE1_AXI_SLAVE_ARES>, |
| <&gcc GCC_PCIE1_AHB_ARES>, |
| <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>; |
| reset-names = "pipe", |
| "sleep", |
| "sticky", |
| "axi_m", |
| "axi_s", |
| "ahb", |
| "axi_m_sticky"; |
| status = "disabled"; |
| }; |
| |
| pcie0: pci@20000000 { |
| compatible = "qcom,pcie-ipq8074-gen3"; |
| reg = <0x20000000 0xf1d>, |
| <0x20000f20 0xa8>, |
| <0x20001000 0x1000>, |
| <0x00080000 0x4000>, |
| <0x20100000 0x1000>; |
| reg-names = "dbi", "elbi", "atu", "parf", "config"; |
| device_type = "pci"; |
| linux,pci-domain = <0>; |
| bus-range = <0x00 0xff>; |
| num-lanes = <1>; |
| max-link-speed = <3>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| phys = <&pcie_phy0>; |
| phy-names = "pciephy"; |
| |
| ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */ |
| <0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */ |
| |
| interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 75 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
| <0 0 0 2 &intc 0 78 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
| <0 0 0 3 &intc 0 79 |
| IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
| <0 0 0 4 &intc 0 83 |
| IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
| |
| clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, |
| <&gcc GCC_PCIE0_AXI_M_CLK>, |
| <&gcc GCC_PCIE0_AXI_S_CLK>, |
| <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, |
| <&gcc GCC_PCIE0_RCHNG_CLK>; |
| clock-names = "iface", |
| "axi_m", |
| "axi_s", |
| "axi_bridge", |
| "rchng"; |
| |
| resets = <&gcc GCC_PCIE0_PIPE_ARES>, |
| <&gcc GCC_PCIE0_SLEEP_ARES>, |
| <&gcc GCC_PCIE0_CORE_STICKY_ARES>, |
| <&gcc GCC_PCIE0_AXI_MASTER_ARES>, |
| <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, |
| <&gcc GCC_PCIE0_AHB_ARES>, |
| <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, |
| <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; |
| reset-names = "pipe", |
| "sleep", |
| "sticky", |
| "axi_m", |
| "axi_s", |
| "ahb", |
| "axi_m_sticky", |
| "axi_s_sticky"; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| thermal-zones { |
| nss-top-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 4>; |
| }; |
| |
| nss0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 5>; |
| }; |
| |
| nss1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 6>; |
| }; |
| |
| wcss-phya0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 7>; |
| }; |
| |
| wcss-phya1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 8>; |
| }; |
| |
| cpu0_thermal: cpu0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 9>; |
| }; |
| |
| cpu1_thermal: cpu1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 10>; |
| }; |
| |
| cpu2_thermal: cpu2-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 11>; |
| }; |
| |
| cpu3_thermal: cpu3-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 12>; |
| }; |
| |
| cluster_thermal: cluster-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 13>; |
| }; |
| |
| wcss-phyb0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 14>; |
| }; |
| |
| wcss-phyb1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens 15>; |
| }; |
| }; |
| }; |
