| [ |
| { |
| "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", |
| "EventCode": "0xC3", |
| "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 128", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 128.", |
| "SampleAfterValue": "1009", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 16", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 16.", |
| "SampleAfterValue": "20011", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 256", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 256.", |
| "SampleAfterValue": "503", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 32", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 32.", |
| "SampleAfterValue": "100007", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 4", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 4.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 512", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 512.", |
| "SampleAfterValue": "101", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 64", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 64.", |
| "SampleAfterValue": "2003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Loads with latency value being above 8", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "PublicDescription": "Loads with latency value being above 8.", |
| "SampleAfterValue": "50021", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only.", |
| "EventCode": "0xCD", |
| "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", |
| "PEBS": "2", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache", |
| "EventCode": "0x05", |
| "EventName": "MISALIGN_MEM_REF.LOADS", |
| "PublicDescription": "Speculative cache-line split load uops dispatched to L1D.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache", |
| "EventCode": "0x05", |
| "EventName": "MISALIGN_MEM_REF.STORES", |
| "PublicDescription": "Speculative cache-line split Store-address uops dispatched to L1D.", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from dram", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x300400244", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts all demand & prefetch data reads that miss the LLC and the data returned from dram", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x300400091", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from dram", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x3004003f7", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts LLC replacements", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x6004001b3", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts demand code reads that miss the LLC and the data returned from dram", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x300400004", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from dram", |
| "EventCode": "0xB7, 0xBB", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "MSRValue": "0x300400001", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Number of any page walk that had a miss in LLC.", |
| "EventCode": "0xBE", |
| "EventName": "PAGE_WALKS.LLC_MISS", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| } |
| ] |
