| [ |
| { |
| "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", |
| "CounterMask": "6", |
| "EventCode": "0xa3", |
| "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x6" |
| }, |
| { |
| "BriefDescription": "Number of machine clears due to memory ordering conflicts.", |
| "EventCode": "0xc3", |
| "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", |
| "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "1009", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "20011", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "503", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100007", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "101", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "2003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.", |
| "Data_LA": "1", |
| "EventCode": "0xcd", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", |
| "SampleAfterValue": "50021", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Demand Data Read requests who miss L3 cache", |
| "EventCode": "0xb0", |
| "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", |
| "PublicDescription": "Demand Data Read requests who miss L3 cache.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x10" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted.", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED", |
| "PublicDescription": "Counts the number of times RTM abort was triggered.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED_EVENTS", |
| "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", |
| "SampleAfterValue": "100003", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED_MEM", |
| "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", |
| "SampleAfterValue": "100003", |
| "UMask": "0x8" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", |
| "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x40" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", |
| "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x20" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution successfully committed", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.COMMIT", |
| "PublicDescription": "Counts the number of times RTM commit succeeded.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of times an RTM execution started.", |
| "EventCode": "0xc9", |
| "EventName": "RTM_RETIRED.START", |
| "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| }, |
| { |
| "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region", |
| "EventCode": "0x5d", |
| "EventName": "TX_EXEC.MISC2", |
| "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded", |
| "EventCode": "0x5d", |
| "EventName": "TX_EXEC.MISC3", |
| "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4" |
| }, |
| { |
| "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CAPACITY_READ", |
| "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads", |
| "SampleAfterValue": "100003", |
| "UMask": "0x80" |
| }, |
| { |
| "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", |
| "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x2" |
| }, |
| { |
| "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", |
| "EventCode": "0x54", |
| "EventName": "TX_MEM.ABORT_CONFLICT", |
| "PublicDescription": "Counts the number of times a TSX line had a cache conflict.", |
| "SampleAfterValue": "100003", |
| "UMask": "0x1" |
| } |
| ] |
