Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Analog Devices AXI DAC IP core

maintainers:
  - Nuno Sa <nuno.sa@analog.com>

description: |
  Analog Devices Generic AXI DAC IP core for interfacing a DAC device
  with a high speed serial (JESD204B/C) or source synchronous parallel
  interface (LVDS/CMOS).
  Usually, some other interface type (i.e SPI) is used as a control
  interface for the actual DAC, while this IP core will interface
  to the data-lines of the DAC and handle the streaming of data from
  memory via DMA into the DAC.

  https://wiki.analog.com/resources/fpga/docs/axi_dac_ip

properties:
  compatible:
    enum:
      - adi,axi-dac-9.1.b

  reg:
    maxItems: 1

  dmas:
    maxItems: 1

  dma-names:
    items:
      - const: tx

  clocks:
    maxItems: 1

  '#io-backend-cells':
    const: 0

required:
  - compatible
  - dmas
  - reg
  - clocks

additionalProperties: false

examples:
  - |
    dac@44a00000 {
        compatible = "adi,axi-dac-9.1.b";
        reg = <0x44a00000 0x10000>;
        dmas = <&tx_dma 0>;
        dma-names = "tx";
        #io-backend-cells = <0>;
        clocks = <&axi_clk>;
    };
...