| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| # Copyright 2023 Realtek Semiconductor Corporation |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Realtek DWC3 USB SoC Controller Glue |
| |
| maintainers: |
| - Stanley Chang <stanley_chang@realtek.com> |
| |
| description: |
| The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0 |
| and USB 3.0 in host or dual-role mode. |
| |
| properties: |
| compatible: |
| items: |
| - enum: |
| - realtek,rtd1295-dwc3 |
| - realtek,rtd1315e-dwc3 |
| - realtek,rtd1319-dwc3 |
| - realtek,rtd1319d-dwc3 |
| - realtek,rtd1395-dwc3 |
| - realtek,rtd1619-dwc3 |
| - realtek,rtd1619b-dwc3 |
| - const: realtek,rtd-dwc3 |
| |
| reg: |
| items: |
| - description: Address and length of register set for wrapper of dwc3 core. |
| - description: Address and length of register set for pm control. |
| |
| '#address-cells': |
| const: 1 |
| |
| '#size-cells': |
| const: 1 |
| |
| ranges: true |
| |
| patternProperties: |
| "^usb@[0-9a-f]+$": |
| $ref: snps,dwc3.yaml# |
| description: Required child node |
| |
| required: |
| - compatible |
| - reg |
| - "#address-cells" |
| - "#size-cells" |
| - ranges |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| usb@98013e00 { |
| compatible = "realtek,rtd1319d-dwc3", "realtek,rtd-dwc3"; |
| reg = <0x98013e00 0x140>, <0x98013f60 0x4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| usb@98050000 { |
| compatible = "snps,dwc3"; |
| reg = <0x98050000 0x9000>; |
| interrupts = <0 94 4>; |
| phys = <&usb2phy &usb3phy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| dr_mode = "otg"; |
| usb-role-switch; |
| role-switch-default-mode = "host"; |
| snps,dis_u2_susphy_quirk; |
| snps,parkmode-disable-ss-quirk; |
| snps,parkmode-disable-hs-quirk; |
| maximum-speed = "high-speed"; |
| }; |
| }; |
