| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /* |
| * Device Tree Source for J784S4 SoC Family |
| * |
| * TRM (SPRUJ43 JULY 2022): https://www.ti.com/lit/zip/spruj52 |
| * |
| * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/soc/ti,sci_pm_domain.h> |
| |
| #include "k3-pinctrl.h" |
| |
| / { |
| model = "Texas Instruments K3 J784S4 SoC"; |
| compatible = "ti,j784s4"; |
| interrupt-parent = <&gic500>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| cpu-map { |
| cluster0: cluster0 { |
| core0 { |
| cpu = <&cpu0>; |
| }; |
| |
| core1 { |
| cpu = <&cpu1>; |
| }; |
| |
| core2 { |
| cpu = <&cpu2>; |
| }; |
| |
| core3 { |
| cpu = <&cpu3>; |
| }; |
| }; |
| |
| cluster1: cluster1 { |
| core0 { |
| cpu = <&cpu4>; |
| }; |
| |
| core1 { |
| cpu = <&cpu5>; |
| }; |
| |
| core2 { |
| cpu = <&cpu6>; |
| }; |
| |
| core3 { |
| cpu = <&cpu7>; |
| }; |
| }; |
| }; |
| |
| cpu0: cpu@0 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x000>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu1: cpu@1 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x001>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu2: cpu@2 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x002>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu3: cpu@3 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x003>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_0>; |
| }; |
| |
| cpu4: cpu@100 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x100>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| cpu5: cpu@101 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x101>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| cpu6: cpu@102 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x102>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_1>; |
| }; |
| |
| cpu7: cpu@103 { |
| compatible = "arm,cortex-a72"; |
| reg = <0x103>; |
| device_type = "cpu"; |
| enable-method = "psci"; |
| i-cache-size = <0xc000>; |
| i-cache-line-size = <64>; |
| i-cache-sets = <256>; |
| d-cache-size = <0x8000>; |
| d-cache-line-size = <64>; |
| d-cache-sets = <256>; |
| next-level-cache = <&L2_1>; |
| }; |
| }; |
| |
| L2_0: l2-cache0 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x200000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| next-level-cache = <&msmc_l3>; |
| }; |
| |
| L2_1: l2-cache1 { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| cache-size = <0x200000>; |
| cache-line-size = <64>; |
| cache-sets = <1024>; |
| next-level-cache = <&msmc_l3>; |
| }; |
| |
| msmc_l3: l3-cache0 { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| |
| psci: psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| }; |
| |
| a72_timer0: timer-cl0-cpu0 { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ |
| <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ |
| <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ |
| <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ |
| }; |
| |
| pmu: pmu { |
| compatible = "arm,cortex-a72-pmu"; |
| /* Recommendation from GIC500 TRM Table A.3 */ |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| cbass_main: bus@100000 { |
| bootph-all; |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ |
| <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ |
| <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */ |
| <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ |
| <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */ |
| <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */ |
| <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/ |
| <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/ |
| <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00800000>, /* PCIe2 Core*/ |
| <0x00 0x0e800000 0x00 0x0e800000 0x00 0x00800000>, /* PCIe3 Core*/ |
| <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */ |
| <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ |
| <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ |
| <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ |
| <0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */ |
| <0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */ |
| <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */ |
| <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ |
| <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ |
| <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */ |
| <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ |
| <0x42 0x00000000 0x42 0x00000000 0x01 0x00000000>, /* PCIe2 DAT1 */ |
| <0x43 0x00000000 0x43 0x00000000 0x01 0x00000000>, /* PCIe3 DAT1 */ |
| <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT0 */ |
| <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT0 */ |
| <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ |
| |
| /* MCUSS_WKUP Range */ |
| <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, |
| <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, |
| <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, |
| <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, |
| <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, |
| <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, |
| <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, |
| <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, |
| <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, |
| <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, |
| <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, |
| <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, |
| <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; |
| |
| cbass_mcu_wakeup: bus@28380000 { |
| bootph-all; |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ |
| <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ |
| <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ |
| <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ |
| <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ |
| <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ |
| <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ |
| <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ |
| <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ |
| <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ |
| <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ |
| <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ |
| <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ |
| }; |
| }; |
| |
| thermal_zones: thermal-zones { |
| #include "k3-j784s4-thermal.dtsi" |
| }; |
| }; |
| |
| /* Now include peripherals from each bus segment */ |
| #include "k3-j784s4-main.dtsi" |
| #include "k3-j784s4-mcu-wakeup.dtsi" |
