| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: Arm SMMUv3 Performance Monitor Counter Group |
| |
| maintainers: |
| - Will Deacon <will@kernel.org> |
| - Robin Murphy <robin.murphy@arm.com> |
| |
| description: | |
| An SMMUv3 may have several Performance Monitor Counter Group (PMCG). |
| They are standalone performance monitoring units that support both |
| architected and IMPLEMENTATION DEFINED event counters. |
| |
| properties: |
| $nodename: |
| pattern: "^pmu@[0-9a-f]*" |
| compatible: |
| oneOf: |
| - items: |
| - const: arm,mmu-600-pmcg |
| - const: arm,smmu-v3-pmcg |
| - const: arm,smmu-v3-pmcg |
| |
| reg: |
| items: |
| - description: Register page 0 |
| - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1 |
| minItems: 1 |
| |
| interrupts: |
| maxItems: 1 |
| |
| msi-parent: true |
| |
| required: |
| - compatible |
| - reg |
| |
| anyOf: |
| - required: |
| - interrupts |
| - required: |
| - msi-parent |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| |
| pmu@2b420000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x2b420000 0x1000>, |
| <0x2b430000 0x1000>; |
| interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>; |
| msi-parent = <&its 0xff0000>; |
| }; |
| |
| pmu@2b440000 { |
| compatible = "arm,smmu-v3-pmcg"; |
| reg = <0x2b440000 0x1000>, |
| <0x2b450000 0x1000>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>; |
| msi-parent = <&its 0xff0000>; |
| }; |
