| // SPDX-License-Identifier: GPL-2.0 OR MIT |
| // |
| // Copyright 2018 Technexion Ltd. |
| // |
| // Author: Wig Cheng <wig.cheng@technexion.com> |
| // Richard Hu <richard.hu@technexion.com> |
| // Tapani Utriainen <tapani@technexion.com> |
| |
| #include <dt-bindings/gpio/gpio.h> |
| |
| / { |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| reg_2p5v: regulator-2p5v { |
| compatible = "regulator-fixed"; |
| regulator-name = "2P5V"; |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <2500000>; |
| regulator-always-on; |
| }; |
| |
| reg_3p3v: regulator-3p3v { |
| compatible = "regulator-fixed"; |
| regulator-name = "3P3V"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| reg_1p8v: regulator-1p8v { |
| compatible = "regulator-fixed"; |
| regulator-name = "1P8V"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| reg_1p5v: regulator-1p5v { |
| compatible = "regulator-fixed"; |
| regulator-name = "1P5V"; |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1500000>; |
| regulator-always-on; |
| }; |
| |
| reg_2p8v: regulator-2p8v { |
| compatible = "regulator-fixed"; |
| regulator-name = "2P8V"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| regulator-always-on; |
| }; |
| |
| reg_usb_otg_vbus: regulator-usb-otg-vbus { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg_vbus>; |
| compatible = "regulator-fixed"; |
| regulator-name = "usb_otg_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; |
| }; |
| |
| codec_osc: clock { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24576000>; |
| }; |
| |
| sound { |
| compatible = "fsl,imx-audio-sgtl5000"; |
| model = "imx6-pico-sgtl5000"; |
| ssi-controller = <&ssi1>; |
| audio-codec = <&sgtl5000>; |
| audio-routing = |
| "MIC_IN", "Mic Jack", |
| "Mic Jack", "Mic Bias", |
| "Headphone Jack", "HP_OUT"; |
| mux-int-port = <1>; |
| mux-ext-port = <3>; |
| }; |
| |
| backlight: backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm4 0 50000 0>; |
| brightness-levels = <0 36 72 108 144 180 216 255>; |
| default-brightness-level = <6>; |
| status = "okay"; |
| }; |
| |
| reg_lcd_3v3: regulator-lcd-3v3 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_lcd>; |
| regulator-name = "lcd-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| lcd_display: disp0 { |
| compatible = "fsl,imx-parallel-display"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ipu1>; |
| status = "okay"; |
| |
| port@0 { |
| reg = <0>; |
| |
| lcd_display_in: endpoint { |
| remote-endpoint = <&ipu1_di0_disp0>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| lcd_display_out: endpoint { |
| remote-endpoint = <&lcd_panel_in>; |
| }; |
| }; |
| }; |
| |
| panel { |
| compatible = "vxt,vl050-8048nt-c01"; |
| backlight = <&backlight>; |
| power-supply = <®_lcd_3v3>; |
| |
| port { |
| lcd_panel_in: endpoint { |
| remote-endpoint = <&lcd_display_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| &audmux { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_audmux>; |
| status = "okay"; |
| }; |
| |
| &can1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| status = "okay"; |
| }; |
| |
| &can2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| status = "okay"; |
| }; |
| |
| &clks { |
| assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, |
| <&clks IMX6QDL_CLK_LDB_DI1_SEL>; |
| assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, |
| <&clks IMX6QDL_CLK_PLL3_USB_OTG>; |
| }; |
| |
| &ecspi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ecspi2>; |
| cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet>; |
| phy-mode = "rgmii-id"; |
| phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; |
| phy-handle = <&phy>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| phy: ethernet-phy@1 { |
| reg = <1>; |
| qca,clk-out-frequency = <125000000>; |
| }; |
| }; |
| }; |
| |
| &hdmi { |
| ddc-i2c-bus = <&i2c2>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| sgtl5000: audio-codec@a { |
| #sound-dai-cells = <0>; |
| reg = <0x0a>; |
| compatible = "fsl,sgtl5000"; |
| clocks = <&codec_osc>; |
| VDDA-supply = <®_2p5v>; |
| VDDIO-supply = <®_1p8v>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| touchscreen@38 { |
| compatible = "edt,edt-ft5x06"; |
| reg = <0x38>; |
| interrupt-parent = <&gpio5>; |
| interrupts = <31 IRQ_TYPE_EDGE_FALLING>; |
| reset-gpios = <&gpio5 27 GPIO_ACTIVE_LOW>; |
| touchscreen-size-x = <800>; |
| touchscreen-size-y = <480>; |
| wakeup-source; |
| }; |
| |
| camera@3c { |
| compatible = "ovti,ov5645"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ov5645>; |
| reg = <0x3c>; |
| clocks = <&clks IMX6QDL_CLK_CKO2>; |
| clock-names = "xclk"; |
| clock-frequency = <24000000>; |
| vdddo-supply = <®_1p8v>; |
| vdda-supply = <®_2p8v>; |
| vddd-supply = <®_1p5v>; |
| enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; |
| reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; |
| |
| port { |
| ov5645_to_mipi_csi2: endpoint { |
| remote-endpoint = <&mipi_csi2_in>; |
| clock-lanes = <0>; |
| data-lanes = <1 2>; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| status = "okay"; |
| }; |
| |
| &ipu1_di0_disp0 { |
| remote-endpoint = <&lcd_display_in>; |
| }; |
| |
| &mipi_csi { |
| status = "okay"; |
| |
| port@0 { |
| reg = <0>; |
| |
| mipi_csi2_in: endpoint { |
| remote-endpoint = <&ov5645_to_mipi_csi2>; |
| clock-lanes = <0>; |
| data-lanes = <1 2>; |
| }; |
| }; |
| }; |
| |
| &pcie { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie_reset>; |
| reset-gpio = <&gpio5 21 GPIO_ACTIVE_LOW>; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1>; |
| status = "okay"; |
| }; |
| |
| &pwm2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm2>; |
| status = "okay"; |
| }; |
| |
| &pwm3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm3>; |
| status = "okay"; |
| }; |
| |
| &pwm4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm4>; |
| status = "okay"; |
| }; |
| |
| &ssi1 { |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &uart2 { /* Bluetooth module */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| uart-has-rtscts; |
| status = "okay"; |
| }; |
| |
| &usbh1 { |
| status = "okay"; |
| }; |
| |
| &usbotg { |
| vbus-supply = <®_usb_otg_vbus>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg>; |
| disable-over-current; |
| dr_mode = "otg"; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| bus-width = <8>; |
| cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { /* Wifi/BT */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| bus-width = <4>; |
| no-1-8-v; |
| keep-power-in-suspend; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| bus-width = <8>; |
| no-1-8-v; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x4001b0b5 /* PICO_P24 */ |
| MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x4001b0b5 /* PICO_P26 */ |
| MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b5 /* PICO_P28 */ |
| MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b0b5 /* PICO_P30 */ |
| MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b0b5 /* PICO_P32 */ |
| MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x4001b0b5 /* PICO_P34 */ |
| MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x4001b0b5 /* PICO_P42 */ |
| MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x4001b0b5 /* PICO_P44 */ |
| MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x4001b0b5 /* PICO_P48 */ |
| >; |
| }; |
| |
| pinctrl_audmux: audmuxgrp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 |
| MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 |
| MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 |
| MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 |
| >; |
| }; |
| |
| pinctrl_ecspi1: ecspi1grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 |
| MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 |
| MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 |
| MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000f0b0 |
| >; |
| }; |
| |
| pinctrl_ecspi2: ecspi2grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1b0b1 |
| MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x1b0b1 |
| MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x1b0b1 |
| MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000f0b0 |
| MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x000f0b0 |
| >; |
| }; |
| |
| pinctrl_enet: enetgrp { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 |
| MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 |
| MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 |
| MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 |
| MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 |
| MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 |
| MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1f0b1 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 |
| MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 |
| MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 |
| MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 |
| MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 |
| >; |
| }; |
| |
| pinctrl_ipu1: ipu1grp { |
| fsl,pins = < |
| MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 |
| MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 |
| MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 |
| MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 |
| MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 |
| MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 |
| MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 |
| MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 |
| MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 |
| MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 |
| MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 |
| MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 |
| MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 |
| MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 |
| MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 |
| MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 |
| MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 |
| MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 |
| MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 |
| MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 |
| MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 |
| MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 |
| MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 |
| MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 |
| MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 |
| MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 |
| MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 |
| MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 |
| MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 |
| >; |
| }; |
| |
| pinctrl_ov5645: ov5645grp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x0b0b0 |
| MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0b0b0 |
| MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 |
| >; |
| }; |
| |
| pinctrl_pcie_reset: pciegrp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x130b0 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_pwm2: pwm2grp { |
| fsl,pins = < |
| MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_pwm3: pwm3grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_pwm4: pwm4grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_reg_lcd: reglcdgrp { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 |
| MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 |
| MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 |
| MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 |
| MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usbotg: usbotggrp { |
| fsl,pins = < |
| MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 |
| >; |
| }; |
| |
| pinctrl_usbotg_vbus: usbotgvbusgrp { |
| fsl,pins = < |
| MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 |
| MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17071 |
| MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 |
| MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 |
| MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 |
| MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 |
| MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 |
| MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 |
| MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 |
| MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 |
| MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 |
| MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 |
| MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 |
| MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 |
| MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 |
| MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 |
| MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 |
| MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0xb0b1 |
| MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 |
| MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 |
| MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 |
| MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 |
| >; |
| }; |
| }; |
