arch/arm64/boot/dts/qcom/ipq8074.dtsi - linux - Git at Google

 /*
  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
  * only version 2 as published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */

 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>

 / {
 	model = "Qualcomm Technologies, Inc. IPQ8074";
 	compatible = "qcom,ipq8074";

 	soc: soc {
 		#address-cells = <0x1>;
 		#size-cells = <0x1>;
 		ranges = <0 0 0 0xffffffff>;
 		compatible = "simple-bus";

 		tlmm: pinctrl@1000000 {
 			compatible = "qcom,ipq8074-pinctrl";
 			reg = <0x1000000 0x300000>;
 			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 			gpio-controller;
 			#gpio-cells = <0x2>;
 			interrupt-controller;
 			#interrupt-cells = <0x2>;

 			serial_4_pins: serial4-pinmux {
 				pins = "gpio23", "gpio24";
 				function = "blsp4_uart1";
 				drive-strength = <8>;
 				bias-disable;
 			};

 			i2c_0_pins: i2c-0-pinmux {
 				pins = "gpio42", "gpio43";
 				function = "blsp1_i2c";
 				drive-strength = <8>;
 				bias-disable;
 			};

 			spi_0_pins: spi-0-pins {
 				pins = "gpio38", "gpio39", "gpio40", "gpio41";
 				function = "blsp0_spi";
 				drive-strength = <8>;
 				bias-disable;
 			};

 			hsuart_pins: hsuart-pins {
 				pins = "gpio46", "gpio47", "gpio48", "gpio49";
 				function = "blsp2_uart";
 				drive-strength = <8>;
 				bias-disable;
 			};

 			qpic_pins: qpic-pins {
 				pins = "gpio1", "gpio3", "gpio4",
 				       "gpio5", "gpio6", "gpio7",
 				       "gpio8", "gpio10", "gpio11",
 				       "gpio12", "gpio13", "gpio14",
 				       "gpio15", "gpio16", "gpio17";
 				function = "qpic";
 				drive-strength = <8>;
 				bias-disable;
 			};
 		};

 		intc: interrupt-controller@b000000 {
 			compatible = "qcom,msm-qgic2";
 			interrupt-controller;
 			#interrupt-cells = <0x3>;
 			reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
 		};

 		timer {
 			compatible = "arm,armv8-timer";
 			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 		};

 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
 			compatible = "arm,armv7-timer-mem";
 			reg = <0xb120000 0x1000>;
 			clock-frequency = <19200000>;

 			frame@b120000 {
 				frame-number = <0>;
 				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb121000 0x1000>,
 				      <0xb122000 0x1000>;
 			};

 			frame@b123000 {
 				frame-number = <1>;
 				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb123000 0x1000>;
 				status = "disabled";
 			};

 			frame@b124000 {
 				frame-number = <2>;
 				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb124000 0x1000>;
 				status = "disabled";
 			};

 			frame@b125000 {
 				frame-number = <3>;
 				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb125000 0x1000>;
 				status = "disabled";
 			};

 			frame@b126000 {
 				frame-number = <4>;
 				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb126000 0x1000>;
 				status = "disabled";
 			};

 			frame@b127000 {
 				frame-number = <5>;
 				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb127000 0x1000>;
 				status = "disabled";
 			};

 			frame@b128000 {
 				frame-number = <6>;
 				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 				reg = <0xb128000 0x1000>;
 				status = "disabled";
 			};
 		};

 		gcc: gcc@1800000 {
 			compatible = "qcom,gcc-ipq8074";
 			reg = <0x1800000 0x80000>;
 			#clock-cells = <0x1>;
 			#reset-cells = <0x1>;
 		};

 		blsp1_uart5: serial@78b3000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78b3000 0x200>;
 			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
 				 <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			pinctrl-0 = <&serial_4_pins>;
 			pinctrl-names = "default";
 			status = "disabled";
 		};

 		blsp_dma: dma@7884000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x7884000 0x2b000>;
 			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
 		};

 		blsp1_uart1: serial@78af000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78af000 0x200>;
 			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
 				 <&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			status = "disabled";
 		};

 		blsp1_uart3: serial@78b1000 {
 			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 			reg = <0x78b1000 0x200>;
 			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
 				<&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			dmas = <&blsp_dma 4>,
 				<&blsp_dma 5>;
 			dma-names = "tx", "rx";
 			pinctrl-0 = <&hsuart_pins>;
 			pinctrl-names = "default";
 			status = "disabled";
 		};

 		blsp1_spi1: spi@78b5000 {
 			compatible = "qcom,spi-qup-v2.2.1";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x78b5000 0x600>;
 			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 			spi-max-frequency = <50000000>;
 			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 				<&gcc GCC_BLSP1_AHB_CLK>;
 			clock-names = "core", "iface";
 			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
 			dma-names = "tx", "rx";
 			pinctrl-0 = <&spi_0_pins>;
 			pinctrl-names = "default";
 			status = "disabled";
 		};

 		blsp1_i2c2: i2c@78b6000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x78b6000 0x600>;
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 			clock-names = "iface", "core";
 			clock-frequency = <400000>;
 			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 			dma-names = "rx", "tx";
 			pinctrl-0 = <&i2c_0_pins>;
 			pinctrl-names = "default";
 			status = "disabled";
 		};

 		blsp1_i2c3: i2c@78b7000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x78b7000 0x600>;
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 			clock-names = "iface", "core";
 			clock-frequency = <100000>;
 			dmas = <&blsp_dma 17>, <&blsp_dma 16>;
 			dma-names = "rx", "tx";
 			status = "disabled";
 		};

 		qpic_bam: dma@7984000 {
 			compatible = "qcom,bam-v1.7.0";
 			reg = <0x7984000 0x1a000>;
 			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&gcc GCC_QPIC_AHB_CLK>;
 			clock-names = "bam_clk";
 			#dma-cells = <1>;
 			qcom,ee = <0>;
 			status = "disabled";
 		};

 		qpic_nand: nand@79b0000 {
 			compatible = "qcom,ipq8074-nand";
 			reg = <0x79b0000 0x10000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			clocks = <&gcc GCC_QPIC_CLK>,
 				 <&gcc GCC_QPIC_AHB_CLK>;
 			clock-names = "core", "aon";

 			dmas = <&qpic_bam 0>,
 			       <&qpic_bam 1>,
 			       <&qpic_bam 2>;
 			dma-names = "tx", "rx", "cmd";
 			pinctrl-0 = <&qpic_pins>;
 			pinctrl-names = "default";
 			status = "disabled";
 		};

 		pcie_phy0: phy@86000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x86000 0x1000>;
 			#phy-cells = <0>;
 			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
 			clock-names = "pipe_clk";
 			clock-output-names = "pcie20_phy0_pipe_clk";

 			resets = <&gcc GCC_PCIE0_PHY_BCR>,
 				<&gcc GCC_PCIE0PHY_PHY_BCR>;
 			reset-names = "phy",
 				      "common";
 			status = "disabled";
 		};

 		pcie0: pci@20000000 {
 			compatible = "qcom,pcie-ipq8074";
 			reg =  <0x20000000 0xf1d
 				0x20000f20 0xa8
 				0x80000 0x2000
 				0x20100000 0x1000>;
 			reg-names = "dbi", "elbi", "parf", "config";
 			device_type = "pci";
 			linux,pci-domain = <0>;
 			bus-range = <0x00 0xff>;
 			num-lanes = <1>;
 			#address-cells = <3>;
 			#size-cells = <2>;

 			phys = <&pcie_phy0>;
 			phy-names = "pciephy";

 			ranges = <0x81000000 0 0x20200000 0x20200000
 				  0 0x100000   /* downstream I/O */
 				  0x82000000 0 0x20300000 0x20300000
 				  0 0xd00000>; /* non-prefetchable memory */

 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 75
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 					<0 0 0 2 &intc 0 78
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 					<0 0 0 3 &intc 0 79
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 					<0 0 0 4 &intc 0 83
 					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

 			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
 				 <&gcc GCC_PCIE0_AXI_M_CLK>,
 				 <&gcc GCC_PCIE0_AXI_S_CLK>,
 				 <&gcc GCC_PCIE0_AHB_CLK>,
 				 <&gcc GCC_PCIE0_AUX_CLK>;

 			clock-names = "iface",
 				      "axi_m",
 				      "axi_s",
 				      "ahb",
 				      "aux";
 			resets = <&gcc GCC_PCIE0_PIPE_ARES>,
 				 <&gcc GCC_PCIE0_SLEEP_ARES>,
 				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
 				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
 				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
 				 <&gcc GCC_PCIE0_AHB_ARES>,
 				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
 			reset-names = "pipe",
 				      "sleep",
 				      "sticky",
 				      "axi_m",
 				      "axi_s",
 				      "ahb",
 				      "axi_m_sticky";
 			status = "disabled";
 		};

 		pcie_phy1: phy@8e000 {
 			compatible = "qcom,ipq8074-qmp-pcie-phy";
 			reg = <0x8e000 0x1000>;
 			#phy-cells = <0>;
 			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
 			clock-names = "pipe_clk";
 			clock-output-names = "pcie20_phy1_pipe_clk";

 			resets = <&gcc GCC_PCIE1_PHY_BCR>,
 				<&gcc GCC_PCIE1PHY_PHY_BCR>;
 			reset-names = "phy",
 				      "common";
 			status = "disabled";
 		};

 		pcie1: pci@10000000 {
 			compatible = "qcom,pcie-ipq8074";
 			reg =  <0x10000000 0xf1d
 				0x10000f20 0xa8
 				0x88000 0x2000
 				0x10100000 0x1000>;
 			reg-names = "dbi", "elbi", "parf", "config";
 			device_type = "pci";
 			linux,pci-domain = <1>;
 			bus-range = <0x00 0xff>;
 			num-lanes = <1>;
 			#address-cells = <3>;
 			#size-cells = <2>;

 			phys = <&pcie_phy1>;
 			phy-names = "pciephy";

 			ranges = <0x81000000 0 0x10200000 0x10200000
 				  0 0x100000   /* downstream I/O */
 				  0x82000000 0 0x10300000 0x10300000
 				  0 0xd00000>; /* non-prefetchable memory */

 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "msi";
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0x7>;
 			interrupt-map = <0 0 0 1 &intc 0 142
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 					<0 0 0 2 &intc 0 143
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 					<0 0 0 3 &intc 0 144
 					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 					<0 0 0 4 &intc 0 145
 					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

 			clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
 				 <&gcc GCC_PCIE1_AXI_M_CLK>,
 				 <&gcc GCC_PCIE1_AXI_S_CLK>,
 				 <&gcc GCC_PCIE1_AHB_CLK>,
 				 <&gcc GCC_PCIE1_AUX_CLK>;
 			clock-names = "iface",
 				      "axi_m",
 				      "axi_s",
 				      "ahb",
 				      "aux";
 			resets = <&gcc GCC_PCIE1_PIPE_ARES>,
 				 <&gcc GCC_PCIE1_SLEEP_ARES>,
 				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
 				 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
 				 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
 				 <&gcc GCC_PCIE1_AHB_ARES>,
 				 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
 			reset-names = "pipe",
 				      "sleep",
 				      "sticky",
 				      "axi_m",
 				      "axi_s",
 				      "ahb",
 				      "axi_m_sticky";
 			status = "disabled";
 		};
 	};

 	cpus {
 		#address-cells = <0x1>;
 		#size-cells = <0x0>;

 		CPU0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			reg = <0x0>;
 			next-level-cache = <&L2_0>;
 			enable-method = "psci";
 		};

 		CPU1: cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			enable-method = "psci";
 			reg = <0x1>;
 			next-level-cache = <&L2_0>;
 		};

 		CPU2: cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			enable-method = "psci";
 			reg = <0x2>;
 			next-level-cache = <&L2_0>;
 		};

 		CPU3: cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53", "arm,armv8";
 			enable-method = "psci";
 			reg = <0x3>;
 			next-level-cache = <&L2_0>;
 		};

 		L2_0: l2-cache {
 			compatible = "cache";
 			cache-level = <0x2>;
 		};
 	};

 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
 	};

 	pmu {
 		compatible = "arm,armv8-pmuv3";
 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};

 	clocks {
 		sleep_clk: sleep_clk {
 			compatible = "fixed-clock";
 			clock-frequency = <32000>;
 			#clock-cells = <0>;
 		};

 		xo: xo {
 			compatible = "fixed-clock";
 			clock-frequency = <19200000>;
 			#clock-cells = <0>;
 		};
 	};
 };
	/*
	* Copyright (c) 2017, The Linux Foundation. All rights reserved.
	*
	* This program is free software; you can redistribute it and/or modify
	* it under the terms of the GNU General Public License version 2 and
	* only version 2 as published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful,
	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	* GNU General Public License for more details.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/qcom,gcc-ipq8074.h>

	/ {
	model = "Qualcomm Technologies, Inc. IPQ8074";
	compatible = "qcom,ipq8074";

	soc: soc {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	tlmm: pinctrl@1000000 {
	compatible = "qcom,ipq8074-pinctrl";
	reg = <0x1000000 0x300000>;
	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	gpio-controller;
	#gpio-cells = <0x2>;
	interrupt-controller;
	#interrupt-cells = <0x2>;

	serial_4_pins: serial4-pinmux {
	pins = "gpio23", "gpio24";
	function = "blsp4_uart1";
	drive-strength = <8>;
	bias-disable;
	};

	i2c_0_pins: i2c-0-pinmux {
	pins = "gpio42", "gpio43";
	function = "blsp1_i2c";
	drive-strength = <8>;
	bias-disable;
	};

	spi_0_pins: spi-0-pins {
	pins = "gpio38", "gpio39", "gpio40", "gpio41";
	function = "blsp0_spi";
	drive-strength = <8>;
	bias-disable;
	};

	hsuart_pins: hsuart-pins {
	pins = "gpio46", "gpio47", "gpio48", "gpio49";
	function = "blsp2_uart";
	drive-strength = <8>;
	bias-disable;
	};

	qpic_pins: qpic-pins {
	pins = "gpio1", "gpio3", "gpio4",
	"gpio5", "gpio6", "gpio7",
	"gpio8", "gpio10", "gpio11",
	"gpio12", "gpio13", "gpio14",
	"gpio15", "gpio16", "gpio17";
	function = "qpic";
	drive-strength = <8>;
	bias-disable;
	};
	};

	intc: interrupt-controller@b000000 {
	compatible = "qcom,msm-qgic2";
	interrupt-controller;
	#interrupt-cells = <0x3>;
	reg = <0xb000000 0x1000>, <0xb002000 0x1000>;
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
	};

	timer@b120000 {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;
	compatible = "arm,armv7-timer-mem";
	reg = <0xb120000 0x1000>;
	clock-frequency = <19200000>;

	frame@b120000 {
	frame-number = <0>;
	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb121000 0x1000>,
	<0xb122000 0x1000>;
	};

	frame@b123000 {
	frame-number = <1>;
	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb123000 0x1000>;
	status = "disabled";
	};

	frame@b124000 {
	frame-number = <2>;
	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb124000 0x1000>;
	status = "disabled";
	};

	frame@b125000 {
	frame-number = <3>;
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb125000 0x1000>;
	status = "disabled";
	};

	frame@b126000 {
	frame-number = <4>;
	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb126000 0x1000>;
	status = "disabled";
	};

	frame@b127000 {
	frame-number = <5>;
	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb127000 0x1000>;
	status = "disabled";
	};

	frame@b128000 {
	frame-number = <6>;
	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	reg = <0xb128000 0x1000>;
	status = "disabled";
	};
	};

	gcc: gcc@1800000 {
	compatible = "qcom,gcc-ipq8074";
	reg = <0x1800000 0x80000>;
	#clock-cells = <0x1>;
	#reset-cells = <0x1>;
	};

	blsp1_uart5: serial@78b3000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b3000 0x200>;
	interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	pinctrl-0 = <&serial_4_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp_dma: dma@7884000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x7884000 0x2b000>;
	interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	};

	blsp1_uart1: serial@78af000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78af000 0x200>;
	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	status = "disabled";
	};

	blsp1_uart3: serial@78b1000 {
	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	reg = <0x78b1000 0x200>;
	interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 4>,
	<&blsp_dma 5>;
	dma-names = "tx", "rx";
	pinctrl-0 = <&hsuart_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_spi1: spi@78b5000 {
	compatible = "qcom,spi-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b5000 0x600>;
	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
	spi-max-frequency = <50000000>;
	clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
	<&gcc GCC_BLSP1_AHB_CLK>;
	clock-names = "core", "iface";
	dmas = <&blsp_dma 12>, <&blsp_dma 13>;
	dma-names = "tx", "rx";
	pinctrl-0 = <&spi_0_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_i2c2: i2c@78b6000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b6000 0x600>;
	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	clock-frequency = <400000>;
	dmas = <&blsp_dma 15>, <&blsp_dma 14>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&i2c_0_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	blsp1_i2c3: i2c@78b7000 {
	compatible = "qcom,i2c-qup-v2.2.1";
	#address-cells = <1>;
	#size-cells = <0>;
	reg = <0x78b7000 0x600>;
	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_BLSP1_AHB_CLK>,
	<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
	clock-names = "iface", "core";
	clock-frequency = <100000>;
	dmas = <&blsp_dma 17>, <&blsp_dma 16>;
	dma-names = "rx", "tx";
	status = "disabled";
	};

	qpic_bam: dma@7984000 {
	compatible = "qcom,bam-v1.7.0";
	reg = <0x7984000 0x1a000>;
	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&gcc GCC_QPIC_AHB_CLK>;
	clock-names = "bam_clk";
	#dma-cells = <1>;
	qcom,ee = <0>;
	status = "disabled";
	};

	qpic_nand: nand@79b0000 {
	compatible = "qcom,ipq8074-nand";
	reg = <0x79b0000 0x10000>;
	#address-cells = <1>;
	#size-cells = <0>;
	clocks = <&gcc GCC_QPIC_CLK>,
	<&gcc GCC_QPIC_AHB_CLK>;
	clock-names = "core", "aon";

	dmas = <&qpic_bam 0>,
	<&qpic_bam 1>,
	<&qpic_bam 2>;
	dma-names = "tx", "rx", "cmd";
	pinctrl-0 = <&qpic_pins>;
	pinctrl-names = "default";
	status = "disabled";
	};

	pcie_phy0: phy@86000 {
	compatible = "qcom,ipq8074-qmp-pcie-phy";
	reg = <0x86000 0x1000>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
	clock-names = "pipe_clk";
	clock-output-names = "pcie20_phy0_pipe_clk";

	resets = <&gcc GCC_PCIE0_PHY_BCR>,
	<&gcc GCC_PCIE0PHY_PHY_BCR>;
	reset-names = "phy",
	"common";
	status = "disabled";
	};

	pcie0: pci@20000000 {
	compatible = "qcom,pcie-ipq8074";
	reg = <0x20000000 0xf1d
	0x20000f20 0xa8
	0x80000 0x2000
	0x20100000 0x1000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <0>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	phys = <&pcie_phy0>;
	phy-names = "pciephy";

	ranges = <0x81000000 0 0x20200000 0x20200000
	0 0x100000 /* downstream I/O */
	0x82000000 0 0x20300000 0x20300000
	0 0xd00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 75
	IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 78
	IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 79
	IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 83
	IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
	<&gcc GCC_PCIE0_AXI_M_CLK>,
	<&gcc GCC_PCIE0_AXI_S_CLK>,
	<&gcc GCC_PCIE0_AHB_CLK>,
	<&gcc GCC_PCIE0_AUX_CLK>;

	clock-names = "iface",
	"axi_m",
	"axi_s",
	"ahb",
	"aux";
	resets = <&gcc GCC_PCIE0_PIPE_ARES>,
	<&gcc GCC_PCIE0_SLEEP_ARES>,
	<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
	<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
	<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
	<&gcc GCC_PCIE0_AHB_ARES>,
	<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
	reset-names = "pipe",
	"sleep",
	"sticky",
	"axi_m",
	"axi_s",
	"ahb",
	"axi_m_sticky";
	status = "disabled";
	};

	pcie_phy1: phy@8e000 {
	compatible = "qcom,ipq8074-qmp-pcie-phy";
	reg = <0x8e000 0x1000>;
	#phy-cells = <0>;
	clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
	clock-names = "pipe_clk";
	clock-output-names = "pcie20_phy1_pipe_clk";

	resets = <&gcc GCC_PCIE1_PHY_BCR>,
	<&gcc GCC_PCIE1PHY_PHY_BCR>;
	reset-names = "phy",
	"common";
	status = "disabled";
	};

	pcie1: pci@10000000 {
	compatible = "qcom,pcie-ipq8074";
	reg = <0x10000000 0xf1d
	0x10000f20 0xa8
	0x88000 0x2000
	0x10100000 0x1000>;
	reg-names = "dbi", "elbi", "parf", "config";
	device_type = "pci";
	linux,pci-domain = <1>;
	bus-range = <0x00 0xff>;
	num-lanes = <1>;
	#address-cells = <3>;
	#size-cells = <2>;

	phys = <&pcie_phy1>;
	phy-names = "pciephy";

	ranges = <0x81000000 0 0x10200000 0x10200000
	0 0x100000 /* downstream I/O */
	0x82000000 0 0x10300000 0x10300000
	0 0xd00000>; /* non-prefetchable memory */

	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "msi";
	#interrupt-cells = <1>;
	interrupt-map-mask = <0 0 0 0x7>;
	interrupt-map = <0 0 0 1 &intc 0 142
	IRQ_TYPE_LEVEL_HIGH>, /* int_a */
	<0 0 0 2 &intc 0 143
	IRQ_TYPE_LEVEL_HIGH>, /* int_b */
	<0 0 0 3 &intc 0 144
	IRQ_TYPE_LEVEL_HIGH>, /* int_c */
	<0 0 0 4 &intc 0 145
	IRQ_TYPE_LEVEL_HIGH>; /* int_d */

	clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
	<&gcc GCC_PCIE1_AXI_M_CLK>,
	<&gcc GCC_PCIE1_AXI_S_CLK>,
	<&gcc GCC_PCIE1_AHB_CLK>,
	<&gcc GCC_PCIE1_AUX_CLK>;
	clock-names = "iface",
	"axi_m",
	"axi_s",
	"ahb",
	"aux";
	resets = <&gcc GCC_PCIE1_PIPE_ARES>,
	<&gcc GCC_PCIE1_SLEEP_ARES>,
	<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
	<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
	<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
	<&gcc GCC_PCIE1_AHB_ARES>,
	<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
	reset-names = "pipe",
	"sleep",
	"sticky",
	"axi_m",
	"axi_s",
	"ahb",
	"axi_m_sticky";
	status = "disabled";
	};
	};

	cpus {
	#address-cells = <0x1>;
	#size-cells = <0x0>;

	CPU0: cpu@0 {
	device_type = "cpu";
	compatible = "arm,cortex-a53", "arm,armv8";
	reg = <0x0>;
	next-level-cache = <&L2_0>;
	enable-method = "psci";
	};

	CPU1: cpu@1 {
	device_type = "cpu";
	compatible = "arm,cortex-a53", "arm,armv8";
	enable-method = "psci";
	reg = <0x1>;
	next-level-cache = <&L2_0>;
	};

	CPU2: cpu@2 {
	device_type = "cpu";
	compatible = "arm,cortex-a53", "arm,armv8";
	enable-method = "psci";
	reg = <0x2>;
	next-level-cache = <&L2_0>;
	};

	CPU3: cpu@3 {
	device_type = "cpu";
	compatible = "arm,cortex-a53", "arm,armv8";
	enable-method = "psci";
	reg = <0x3>;
	next-level-cache = <&L2_0>;
	};

	L2_0: l2-cache {
	compatible = "cache";
	cache-level = <0x2>;
	};
	};

	psci {
	compatible = "arm,psci-1.0";
	method = "smc";
	};

	pmu {
	compatible = "arm,armv8-pmuv3";
	interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	};

	clocks {
	sleep_clk: sleep_clk {
	compatible = "fixed-clock";
	clock-frequency = <32000>;
	#clock-cells = <0>;
	};

	xo: xo {
	compatible = "fixed-clock";
	clock-frequency = <19200000>;
	#clock-cells = <0>;
	};
	};
	};