| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_NIC0_QM1_REGS_H_ |
| #define ASIC_REG_NIC0_QM1_REGS_H_ |
| |
| /* |
| ***************************************** |
| * NIC0_QM1 (Prototype: QMAN) |
| ***************************************** |
| */ |
| |
| #define mmNIC0_QM1_GLBL_CFG0 0xCE2000 |
| |
| #define mmNIC0_QM1_GLBL_CFG1 0xCE2004 |
| |
| #define mmNIC0_QM1_GLBL_PROT 0xCE2008 |
| |
| #define mmNIC0_QM1_GLBL_ERR_CFG 0xCE200C |
| |
| #define mmNIC0_QM1_GLBL_SECURE_PROPS_0 0xCE2010 |
| |
| #define mmNIC0_QM1_GLBL_SECURE_PROPS_1 0xCE2014 |
| |
| #define mmNIC0_QM1_GLBL_SECURE_PROPS_2 0xCE2018 |
| |
| #define mmNIC0_QM1_GLBL_SECURE_PROPS_3 0xCE201C |
| |
| #define mmNIC0_QM1_GLBL_SECURE_PROPS_4 0xCE2020 |
| |
| #define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_0 0xCE2024 |
| |
| #define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_1 0xCE2028 |
| |
| #define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_2 0xCE202C |
| |
| #define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_3 0xCE2030 |
| |
| #define mmNIC0_QM1_GLBL_NON_SECURE_PROPS_4 0xCE2034 |
| |
| #define mmNIC0_QM1_GLBL_STS0 0xCE2038 |
| |
| #define mmNIC0_QM1_GLBL_STS1_0 0xCE2040 |
| |
| #define mmNIC0_QM1_GLBL_STS1_1 0xCE2044 |
| |
| #define mmNIC0_QM1_GLBL_STS1_2 0xCE2048 |
| |
| #define mmNIC0_QM1_GLBL_STS1_3 0xCE204C |
| |
| #define mmNIC0_QM1_GLBL_STS1_4 0xCE2050 |
| |
| #define mmNIC0_QM1_GLBL_MSG_EN_0 0xCE2054 |
| |
| #define mmNIC0_QM1_GLBL_MSG_EN_1 0xCE2058 |
| |
| #define mmNIC0_QM1_GLBL_MSG_EN_2 0xCE205C |
| |
| #define mmNIC0_QM1_GLBL_MSG_EN_3 0xCE2060 |
| |
| #define mmNIC0_QM1_GLBL_MSG_EN_4 0xCE2068 |
| |
| #define mmNIC0_QM1_PQ_BASE_LO_0 0xCE2070 |
| |
| #define mmNIC0_QM1_PQ_BASE_LO_1 0xCE2074 |
| |
| #define mmNIC0_QM1_PQ_BASE_LO_2 0xCE2078 |
| |
| #define mmNIC0_QM1_PQ_BASE_LO_3 0xCE207C |
| |
| #define mmNIC0_QM1_PQ_BASE_HI_0 0xCE2080 |
| |
| #define mmNIC0_QM1_PQ_BASE_HI_1 0xCE2084 |
| |
| #define mmNIC0_QM1_PQ_BASE_HI_2 0xCE2088 |
| |
| #define mmNIC0_QM1_PQ_BASE_HI_3 0xCE208C |
| |
| #define mmNIC0_QM1_PQ_SIZE_0 0xCE2090 |
| |
| #define mmNIC0_QM1_PQ_SIZE_1 0xCE2094 |
| |
| #define mmNIC0_QM1_PQ_SIZE_2 0xCE2098 |
| |
| #define mmNIC0_QM1_PQ_SIZE_3 0xCE209C |
| |
| #define mmNIC0_QM1_PQ_PI_0 0xCE20A0 |
| |
| #define mmNIC0_QM1_PQ_PI_1 0xCE20A4 |
| |
| #define mmNIC0_QM1_PQ_PI_2 0xCE20A8 |
| |
| #define mmNIC0_QM1_PQ_PI_3 0xCE20AC |
| |
| #define mmNIC0_QM1_PQ_CI_0 0xCE20B0 |
| |
| #define mmNIC0_QM1_PQ_CI_1 0xCE20B4 |
| |
| #define mmNIC0_QM1_PQ_CI_2 0xCE20B8 |
| |
| #define mmNIC0_QM1_PQ_CI_3 0xCE20BC |
| |
| #define mmNIC0_QM1_PQ_CFG0_0 0xCE20C0 |
| |
| #define mmNIC0_QM1_PQ_CFG0_1 0xCE20C4 |
| |
| #define mmNIC0_QM1_PQ_CFG0_2 0xCE20C8 |
| |
| #define mmNIC0_QM1_PQ_CFG0_3 0xCE20CC |
| |
| #define mmNIC0_QM1_PQ_CFG1_0 0xCE20D0 |
| |
| #define mmNIC0_QM1_PQ_CFG1_1 0xCE20D4 |
| |
| #define mmNIC0_QM1_PQ_CFG1_2 0xCE20D8 |
| |
| #define mmNIC0_QM1_PQ_CFG1_3 0xCE20DC |
| |
| #define mmNIC0_QM1_PQ_ARUSER_31_11_0 0xCE20E0 |
| |
| #define mmNIC0_QM1_PQ_ARUSER_31_11_1 0xCE20E4 |
| |
| #define mmNIC0_QM1_PQ_ARUSER_31_11_2 0xCE20E8 |
| |
| #define mmNIC0_QM1_PQ_ARUSER_31_11_3 0xCE20EC |
| |
| #define mmNIC0_QM1_PQ_STS0_0 0xCE20F0 |
| |
| #define mmNIC0_QM1_PQ_STS0_1 0xCE20F4 |
| |
| #define mmNIC0_QM1_PQ_STS0_2 0xCE20F8 |
| |
| #define mmNIC0_QM1_PQ_STS0_3 0xCE20FC |
| |
| #define mmNIC0_QM1_PQ_STS1_0 0xCE2100 |
| |
| #define mmNIC0_QM1_PQ_STS1_1 0xCE2104 |
| |
| #define mmNIC0_QM1_PQ_STS1_2 0xCE2108 |
| |
| #define mmNIC0_QM1_PQ_STS1_3 0xCE210C |
| |
| #define mmNIC0_QM1_CQ_CFG0_0 0xCE2110 |
| |
| #define mmNIC0_QM1_CQ_CFG0_1 0xCE2114 |
| |
| #define mmNIC0_QM1_CQ_CFG0_2 0xCE2118 |
| |
| #define mmNIC0_QM1_CQ_CFG0_3 0xCE211C |
| |
| #define mmNIC0_QM1_CQ_CFG0_4 0xCE2120 |
| |
| #define mmNIC0_QM1_CQ_CFG1_0 0xCE2124 |
| |
| #define mmNIC0_QM1_CQ_CFG1_1 0xCE2128 |
| |
| #define mmNIC0_QM1_CQ_CFG1_2 0xCE212C |
| |
| #define mmNIC0_QM1_CQ_CFG1_3 0xCE2130 |
| |
| #define mmNIC0_QM1_CQ_CFG1_4 0xCE2134 |
| |
| #define mmNIC0_QM1_CQ_ARUSER_31_11_0 0xCE2138 |
| |
| #define mmNIC0_QM1_CQ_ARUSER_31_11_1 0xCE213C |
| |
| #define mmNIC0_QM1_CQ_ARUSER_31_11_2 0xCE2140 |
| |
| #define mmNIC0_QM1_CQ_ARUSER_31_11_3 0xCE2144 |
| |
| #define mmNIC0_QM1_CQ_ARUSER_31_11_4 0xCE2148 |
| |
| #define mmNIC0_QM1_CQ_STS0_0 0xCE214C |
| |
| #define mmNIC0_QM1_CQ_STS0_1 0xCE2150 |
| |
| #define mmNIC0_QM1_CQ_STS0_2 0xCE2154 |
| |
| #define mmNIC0_QM1_CQ_STS0_3 0xCE2158 |
| |
| #define mmNIC0_QM1_CQ_STS0_4 0xCE215C |
| |
| #define mmNIC0_QM1_CQ_STS1_0 0xCE2160 |
| |
| #define mmNIC0_QM1_CQ_STS1_1 0xCE2164 |
| |
| #define mmNIC0_QM1_CQ_STS1_2 0xCE2168 |
| |
| #define mmNIC0_QM1_CQ_STS1_3 0xCE216C |
| |
| #define mmNIC0_QM1_CQ_STS1_4 0xCE2170 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_0 0xCE2174 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_0 0xCE2178 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_0 0xCE217C |
| |
| #define mmNIC0_QM1_CQ_CTL_0 0xCE2180 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_1 0xCE2184 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_1 0xCE2188 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_1 0xCE218C |
| |
| #define mmNIC0_QM1_CQ_CTL_1 0xCE2190 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_2 0xCE2194 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_2 0xCE2198 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_2 0xCE219C |
| |
| #define mmNIC0_QM1_CQ_CTL_2 0xCE21A0 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_3 0xCE21A4 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_3 0xCE21A8 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_3 0xCE21AC |
| |
| #define mmNIC0_QM1_CQ_CTL_3 0xCE21B0 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_4 0xCE21B4 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_4 0xCE21B8 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_4 0xCE21BC |
| |
| #define mmNIC0_QM1_CQ_CTL_4 0xCE21C0 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_STS_0 0xCE21C4 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_STS_1 0xCE21C8 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_STS_2 0xCE21CC |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_STS_3 0xCE21D0 |
| |
| #define mmNIC0_QM1_CQ_PTR_LO_STS_4 0xCE21D4 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_STS_0 0xCE21D8 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_STS_1 0xCE21DC |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_STS_2 0xCE21E0 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_STS_3 0xCE21E4 |
| |
| #define mmNIC0_QM1_CQ_PTR_HI_STS_4 0xCE21E8 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_STS_0 0xCE21EC |
| |
| #define mmNIC0_QM1_CQ_TSIZE_STS_1 0xCE21F0 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_STS_2 0xCE21F4 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_STS_3 0xCE21F8 |
| |
| #define mmNIC0_QM1_CQ_TSIZE_STS_4 0xCE21FC |
| |
| #define mmNIC0_QM1_CQ_CTL_STS_0 0xCE2200 |
| |
| #define mmNIC0_QM1_CQ_CTL_STS_1 0xCE2204 |
| |
| #define mmNIC0_QM1_CQ_CTL_STS_2 0xCE2208 |
| |
| #define mmNIC0_QM1_CQ_CTL_STS_3 0xCE220C |
| |
| #define mmNIC0_QM1_CQ_CTL_STS_4 0xCE2210 |
| |
| #define mmNIC0_QM1_CQ_IFIFO_CNT_0 0xCE2214 |
| |
| #define mmNIC0_QM1_CQ_IFIFO_CNT_1 0xCE2218 |
| |
| #define mmNIC0_QM1_CQ_IFIFO_CNT_2 0xCE221C |
| |
| #define mmNIC0_QM1_CQ_IFIFO_CNT_3 0xCE2220 |
| |
| #define mmNIC0_QM1_CQ_IFIFO_CNT_4 0xCE2224 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_0 0xCE2228 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_1 0xCE222C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_2 0xCE2230 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_3 0xCE2234 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_LO_4 0xCE2238 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_0 0xCE223C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_1 0xCE2240 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_2 0xCE2244 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_3 0xCE2248 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE0_ADDR_HI_4 0xCE224C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_0 0xCE2250 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_1 0xCE2254 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_2 0xCE2258 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_3 0xCE225C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_LO_4 0xCE2260 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_0 0xCE2264 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_1 0xCE2268 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_2 0xCE226C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_3 0xCE2270 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE1_ADDR_HI_4 0xCE2274 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_0 0xCE2278 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_1 0xCE227C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_2 0xCE2280 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_3 0xCE2284 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_LO_4 0xCE2288 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_0 0xCE228C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_1 0xCE2290 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_2 0xCE2294 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_3 0xCE2298 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE2_ADDR_HI_4 0xCE229C |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_0 0xCE22A0 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_1 0xCE22A4 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_2 0xCE22A8 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_3 0xCE22AC |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_LO_4 0xCE22B0 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_0 0xCE22B4 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_1 0xCE22B8 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_2 0xCE22BC |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_3 0xCE22C0 |
| |
| #define mmNIC0_QM1_CP_MSG_BASE3_ADDR_HI_4 0xCE22C4 |
| |
| #define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_0 0xCE22C8 |
| |
| #define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_1 0xCE22CC |
| |
| #define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_2 0xCE22D0 |
| |
| #define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_3 0xCE22D4 |
| |
| #define mmNIC0_QM1_CP_LDMA_TSIZE_OFFSET_4 0xCE22D8 |
| |
| #define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_0 0xCE22E0 |
| |
| #define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_1 0xCE22E4 |
| |
| #define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_2 0xCE22E8 |
| |
| #define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_3 0xCE22EC |
| |
| #define mmNIC0_QM1_CP_LDMA_SRC_BASE_LO_OFFSET_4 0xCE22F0 |
| |
| #define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_0 0xCE22F4 |
| |
| #define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_1 0xCE22F8 |
| |
| #define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_2 0xCE22FC |
| |
| #define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_3 0xCE2300 |
| |
| #define mmNIC0_QM1_CP_LDMA_DST_BASE_LO_OFFSET_4 0xCE2304 |
| |
| #define mmNIC0_QM1_CP_FENCE0_RDATA_0 0xCE2308 |
| |
| #define mmNIC0_QM1_CP_FENCE0_RDATA_1 0xCE230C |
| |
| #define mmNIC0_QM1_CP_FENCE0_RDATA_2 0xCE2310 |
| |
| #define mmNIC0_QM1_CP_FENCE0_RDATA_3 0xCE2314 |
| |
| #define mmNIC0_QM1_CP_FENCE0_RDATA_4 0xCE2318 |
| |
| #define mmNIC0_QM1_CP_FENCE1_RDATA_0 0xCE231C |
| |
| #define mmNIC0_QM1_CP_FENCE1_RDATA_1 0xCE2320 |
| |
| #define mmNIC0_QM1_CP_FENCE1_RDATA_2 0xCE2324 |
| |
| #define mmNIC0_QM1_CP_FENCE1_RDATA_3 0xCE2328 |
| |
| #define mmNIC0_QM1_CP_FENCE1_RDATA_4 0xCE232C |
| |
| #define mmNIC0_QM1_CP_FENCE2_RDATA_0 0xCE2330 |
| |
| #define mmNIC0_QM1_CP_FENCE2_RDATA_1 0xCE2334 |
| |
| #define mmNIC0_QM1_CP_FENCE2_RDATA_2 0xCE2338 |
| |
| #define mmNIC0_QM1_CP_FENCE2_RDATA_3 0xCE233C |
| |
| #define mmNIC0_QM1_CP_FENCE2_RDATA_4 0xCE2340 |
| |
| #define mmNIC0_QM1_CP_FENCE3_RDATA_0 0xCE2344 |
| |
| #define mmNIC0_QM1_CP_FENCE3_RDATA_1 0xCE2348 |
| |
| #define mmNIC0_QM1_CP_FENCE3_RDATA_2 0xCE234C |
| |
| #define mmNIC0_QM1_CP_FENCE3_RDATA_3 0xCE2350 |
| |
| #define mmNIC0_QM1_CP_FENCE3_RDATA_4 0xCE2354 |
| |
| #define mmNIC0_QM1_CP_FENCE0_CNT_0 0xCE2358 |
| |
| #define mmNIC0_QM1_CP_FENCE0_CNT_1 0xCE235C |
| |
| #define mmNIC0_QM1_CP_FENCE0_CNT_2 0xCE2360 |
| |
| #define mmNIC0_QM1_CP_FENCE0_CNT_3 0xCE2364 |
| |
| #define mmNIC0_QM1_CP_FENCE0_CNT_4 0xCE2368 |
| |
| #define mmNIC0_QM1_CP_FENCE1_CNT_0 0xCE236C |
| |
| #define mmNIC0_QM1_CP_FENCE1_CNT_1 0xCE2370 |
| |
| #define mmNIC0_QM1_CP_FENCE1_CNT_2 0xCE2374 |
| |
| #define mmNIC0_QM1_CP_FENCE1_CNT_3 0xCE2378 |
| |
| #define mmNIC0_QM1_CP_FENCE1_CNT_4 0xCE237C |
| |
| #define mmNIC0_QM1_CP_FENCE2_CNT_0 0xCE2380 |
| |
| #define mmNIC0_QM1_CP_FENCE2_CNT_1 0xCE2384 |
| |
| #define mmNIC0_QM1_CP_FENCE2_CNT_2 0xCE2388 |
| |
| #define mmNIC0_QM1_CP_FENCE2_CNT_3 0xCE238C |
| |
| #define mmNIC0_QM1_CP_FENCE2_CNT_4 0xCE2390 |
| |
| #define mmNIC0_QM1_CP_FENCE3_CNT_0 0xCE2394 |
| |
| #define mmNIC0_QM1_CP_FENCE3_CNT_1 0xCE2398 |
| |
| #define mmNIC0_QM1_CP_FENCE3_CNT_2 0xCE239C |
| |
| #define mmNIC0_QM1_CP_FENCE3_CNT_3 0xCE23A0 |
| |
| #define mmNIC0_QM1_CP_FENCE3_CNT_4 0xCE23A4 |
| |
| #define mmNIC0_QM1_CP_STS_0 0xCE23A8 |
| |
| #define mmNIC0_QM1_CP_STS_1 0xCE23AC |
| |
| #define mmNIC0_QM1_CP_STS_2 0xCE23B0 |
| |
| #define mmNIC0_QM1_CP_STS_3 0xCE23B4 |
| |
| #define mmNIC0_QM1_CP_STS_4 0xCE23B8 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_LO_0 0xCE23BC |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_LO_1 0xCE23C0 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_LO_2 0xCE23C4 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_LO_3 0xCE23C8 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_LO_4 0xCE23CC |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_HI_0 0xCE23D0 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_HI_1 0xCE23D4 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_HI_2 0xCE23D8 |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_HI_3 0xCE23DC |
| |
| #define mmNIC0_QM1_CP_CURRENT_INST_HI_4 0xCE23E0 |
| |
| #define mmNIC0_QM1_CP_BARRIER_CFG_0 0xCE23F4 |
| |
| #define mmNIC0_QM1_CP_BARRIER_CFG_1 0xCE23F8 |
| |
| #define mmNIC0_QM1_CP_BARRIER_CFG_2 0xCE23FC |
| |
| #define mmNIC0_QM1_CP_BARRIER_CFG_3 0xCE2400 |
| |
| #define mmNIC0_QM1_CP_BARRIER_CFG_4 0xCE2404 |
| |
| #define mmNIC0_QM1_CP_DBG_0_0 0xCE2408 |
| |
| #define mmNIC0_QM1_CP_DBG_0_1 0xCE240C |
| |
| #define mmNIC0_QM1_CP_DBG_0_2 0xCE2410 |
| |
| #define mmNIC0_QM1_CP_DBG_0_3 0xCE2414 |
| |
| #define mmNIC0_QM1_CP_DBG_0_4 0xCE2418 |
| |
| #define mmNIC0_QM1_CP_ARUSER_31_11_0 0xCE241C |
| |
| #define mmNIC0_QM1_CP_ARUSER_31_11_1 0xCE2420 |
| |
| #define mmNIC0_QM1_CP_ARUSER_31_11_2 0xCE2424 |
| |
| #define mmNIC0_QM1_CP_ARUSER_31_11_3 0xCE2428 |
| |
| #define mmNIC0_QM1_CP_ARUSER_31_11_4 0xCE242C |
| |
| #define mmNIC0_QM1_CP_AWUSER_31_11_0 0xCE2430 |
| |
| #define mmNIC0_QM1_CP_AWUSER_31_11_1 0xCE2434 |
| |
| #define mmNIC0_QM1_CP_AWUSER_31_11_2 0xCE2438 |
| |
| #define mmNIC0_QM1_CP_AWUSER_31_11_3 0xCE243C |
| |
| #define mmNIC0_QM1_CP_AWUSER_31_11_4 0xCE2440 |
| |
| #define mmNIC0_QM1_ARB_CFG_0 0xCE2A00 |
| |
| #define mmNIC0_QM1_ARB_CHOISE_Q_PUSH 0xCE2A04 |
| |
| #define mmNIC0_QM1_ARB_WRR_WEIGHT_0 0xCE2A08 |
| |
| #define mmNIC0_QM1_ARB_WRR_WEIGHT_1 0xCE2A0C |
| |
| #define mmNIC0_QM1_ARB_WRR_WEIGHT_2 0xCE2A10 |
| |
| #define mmNIC0_QM1_ARB_WRR_WEIGHT_3 0xCE2A14 |
| |
| #define mmNIC0_QM1_ARB_CFG_1 0xCE2A18 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_0 0xCE2A20 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_1 0xCE2A24 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_2 0xCE2A28 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_3 0xCE2A2C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_4 0xCE2A30 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_5 0xCE2A34 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_6 0xCE2A38 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_7 0xCE2A3C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_8 0xCE2A40 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_9 0xCE2A44 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_10 0xCE2A48 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_11 0xCE2A4C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_12 0xCE2A50 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_13 0xCE2A54 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_14 0xCE2A58 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_15 0xCE2A5C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_16 0xCE2A60 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_17 0xCE2A64 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_18 0xCE2A68 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_19 0xCE2A6C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_20 0xCE2A70 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_21 0xCE2A74 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_22 0xCE2A78 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_23 0xCE2A7C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_24 0xCE2A80 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_25 0xCE2A84 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_26 0xCE2A88 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_27 0xCE2A8C |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_28 0xCE2A90 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_29 0xCE2A94 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_30 0xCE2A98 |
| |
| #define mmNIC0_QM1_ARB_MST_AVAIL_CRED_31 0xCE2A9C |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_INC 0xCE2AA0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_0 0xCE2AA4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_1 0xCE2AA8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_2 0xCE2AAC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_3 0xCE2AB0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_4 0xCE2AB4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_5 0xCE2AB8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_6 0xCE2ABC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_7 0xCE2AC0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_8 0xCE2AC4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_9 0xCE2AC8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_10 0xCE2ACC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_11 0xCE2AD0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_12 0xCE2AD4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_13 0xCE2AD8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_14 0xCE2ADC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_15 0xCE2AE0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_16 0xCE2AE4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_17 0xCE2AE8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_18 0xCE2AEC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_19 0xCE2AF0 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_20 0xCE2AF4 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_21 0xCE2AF8 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_22 0xCE2AFC |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_23 0xCE2B00 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_24 0xCE2B04 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_25 0xCE2B08 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_26 0xCE2B0C |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_27 0xCE2B10 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_28 0xCE2B14 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_29 0xCE2B18 |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_30 0xCE2B1C |
| |
| #define mmNIC0_QM1_ARB_MST_CHOISE_PUSH_OFST_31 0xCE2B20 |
| |
| #define mmNIC0_QM1_ARB_SLV_MASTER_INC_CRED_OFST 0xCE2B28 |
| |
| #define mmNIC0_QM1_ARB_MST_SLAVE_EN 0xCE2B2C |
| |
| #define mmNIC0_QM1_ARB_MST_QUIET_PER 0xCE2B34 |
| |
| #define mmNIC0_QM1_ARB_SLV_CHOISE_WDT 0xCE2B38 |
| |
| #define mmNIC0_QM1_ARB_SLV_ID 0xCE2B3C |
| |
| #define mmNIC0_QM1_ARB_MSG_MAX_INFLIGHT 0xCE2B44 |
| |
| #define mmNIC0_QM1_ARB_MSG_AWUSER_31_11 0xCE2B48 |
| |
| #define mmNIC0_QM1_ARB_MSG_AWUSER_SEC_PROP 0xCE2B4C |
| |
| #define mmNIC0_QM1_ARB_MSG_AWUSER_NON_SEC_PROP 0xCE2B50 |
| |
| #define mmNIC0_QM1_ARB_BASE_LO 0xCE2B54 |
| |
| #define mmNIC0_QM1_ARB_BASE_HI 0xCE2B58 |
| |
| #define mmNIC0_QM1_ARB_STATE_STS 0xCE2B80 |
| |
| #define mmNIC0_QM1_ARB_CHOISE_FULLNESS_STS 0xCE2B84 |
| |
| #define mmNIC0_QM1_ARB_MSG_STS 0xCE2B88 |
| |
| #define mmNIC0_QM1_ARB_SLV_CHOISE_Q_HEAD 0xCE2B8C |
| |
| #define mmNIC0_QM1_ARB_ERR_CAUSE 0xCE2B9C |
| |
| #define mmNIC0_QM1_ARB_ERR_MSG_EN 0xCE2BA0 |
| |
| #define mmNIC0_QM1_ARB_ERR_STS_DRP 0xCE2BA8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_0 0xCE2BB0 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_1 0xCE2BB4 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_2 0xCE2BB8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_3 0xCE2BBC |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_4 0xCE2BC0 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_5 0xCE2BC4 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_6 0xCE2BC8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_7 0xCE2BCC |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_8 0xCE2BD0 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_9 0xCE2BD4 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_10 0xCE2BD8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_11 0xCE2BDC |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_12 0xCE2BE0 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_13 0xCE2BE4 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_14 0xCE2BE8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_15 0xCE2BEC |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_16 0xCE2BF0 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_17 0xCE2BF4 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_18 0xCE2BF8 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_19 0xCE2BFC |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_20 0xCE2C00 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_21 0xCE2C04 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_22 0xCE2C08 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_23 0xCE2C0C |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_24 0xCE2C10 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_25 0xCE2C14 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_26 0xCE2C18 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_27 0xCE2C1C |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_28 0xCE2C20 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_29 0xCE2C24 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_30 0xCE2C28 |
| |
| #define mmNIC0_QM1_ARB_MST_CRED_STS_31 0xCE2C2C |
| |
| #define mmNIC0_QM1_CGM_CFG 0xCE2C70 |
| |
| #define mmNIC0_QM1_CGM_STS 0xCE2C74 |
| |
| #define mmNIC0_QM1_CGM_CFG1 0xCE2C78 |
| |
| #define mmNIC0_QM1_LOCAL_RANGE_BASE 0xCE2C80 |
| |
| #define mmNIC0_QM1_LOCAL_RANGE_SIZE 0xCE2C84 |
| |
| #define mmNIC0_QM1_CSMR_STRICT_PRIO_CFG 0xCE2C90 |
| |
| #define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_1 0xCE2C94 |
| |
| #define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_0 0xCE2C98 |
| |
| #define mmNIC0_QM1_LBW_WR_RATE_LIM_CFG_1 0xCE2C9C |
| |
| #define mmNIC0_QM1_HBW_RD_RATE_LIM_CFG_0 0xCE2CA0 |
| |
| #define mmNIC0_QM1_GLBL_AXCACHE 0xCE2CA4 |
| |
| #define mmNIC0_QM1_IND_GW_APB_CFG 0xCE2CB0 |
| |
| #define mmNIC0_QM1_IND_GW_APB_WDATA 0xCE2CB4 |
| |
| #define mmNIC0_QM1_IND_GW_APB_RDATA 0xCE2CB8 |
| |
| #define mmNIC0_QM1_IND_GW_APB_STATUS 0xCE2CBC |
| |
| #define mmNIC0_QM1_GLBL_ERR_ADDR_LO 0xCE2CD0 |
| |
| #define mmNIC0_QM1_GLBL_ERR_ADDR_HI 0xCE2CD4 |
| |
| #define mmNIC0_QM1_GLBL_ERR_WDATA 0xCE2CD8 |
| |
| #define mmNIC0_QM1_GLBL_MEM_INIT_BUSY 0xCE2D00 |
| |
| #endif /* ASIC_REG_NIC0_QM1_REGS_H_ */ |
