| # SPDX-License-Identifier: GPL-2.0 |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| |
| title: ARM Generic Interrupt Controller v1 and v2 |
| |
| maintainers: |
| - Marc Zyngier <marc.zyngier@arm.com> |
| |
| description: |+ |
| ARM SMP cores are often associated with a GIC, providing per processor |
| interrupts (PPI), shared processor interrupts (SPI) and software |
| generated interrupts (SGI). |
| |
| Primary GIC is attached directly to the CPU and typically has PPIs and SGIs. |
| Secondary GICs are cascaded into the upward interrupt controller and do not |
| have PPIs or SGIs. |
| |
| allOf: |
| - $ref: /schemas/interrupt-controller.yaml# |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - enum: |
| - arm,arm11mp-gic |
| - arm,cortex-a15-gic |
| - arm,cortex-a7-gic |
| - arm,cortex-a5-gic |
| - arm,cortex-a9-gic |
| - arm,eb11mp-gic |
| - arm,gic-400 |
| - arm,pl390 |
| - arm,tc11mp-gic |
| - qcom,msm-8660-qgic |
| - qcom,msm-qgic2 |
| |
| - items: |
| - const: arm,gic-400 |
| - enum: |
| - arm,cortex-a15-gic |
| - arm,cortex-a7-gic |
| |
| - items: |
| - const: arm,arm1176jzf-devchip-gic |
| - const: arm,arm11mp-gic |
| |
| - items: |
| - const: brcm,brahma-b15-gic |
| - const: arm,cortex-a15-gic |
| |
| - oneOf: |
| - const: nvidia,tegra210-agic |
| - items: |
| - enum: |
| - nvidia,tegra186-agic |
| - nvidia,tegra194-agic |
| - const: nvidia,tegra210-agic |
| |
| interrupt-controller: true |
| |
| "#address-cells": |
| enum: [ 0, 1 ] |
| "#size-cells": |
| const: 1 |
| |
| "#interrupt-cells": |
| const: 3 |
| description: | |
| The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI |
| interrupts. |
| |
| The 2nd cell contains the interrupt number for the interrupt type. |
| SPI interrupts are in the range [0-987]. PPI interrupts are in the |
| range [0-15]. |
| |
| The 3rd cell is the flags, encoded as follows: |
| bits[3:0] trigger type and level flags. |
| 1 = low-to-high edge triggered |
| 2 = high-to-low edge triggered (invalid for SPIs) |
| 4 = active high level-sensitive |
| 8 = active low level-sensitive (invalid for SPIs). |
| bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of |
| the 8 possible cpus attached to the GIC. A bit set to '1' indicated |
| the interrupt is wired to that CPU. Only valid for PPI interrupts. |
| Also note that the configurability of PPI interrupts is IMPLEMENTATION |
| DEFINED and as such not guaranteed to be present (most SoC available |
| in 2014 seem to ignore the setting of this flag and use the hardware |
| default value). |
| |
| reg: |
| description: | |
| Specifies base physical address(s) and size of the GIC registers. The |
| first region is the GIC distributor register base and size. The 2nd region |
| is the GIC cpu interface register base and size. |
| |
| For GICv2 with virtualization extensions, additional regions are |
| required for specifying the base physical address and size of the VGIC |
| registers. The first additional region is the GIC virtual interface |
| control register base and size. The 2nd additional region is the GIC |
| virtual cpu interface register base and size. |
| minItems: 2 |
| maxItems: 4 |
| |
| ranges: true |
| |
| interrupts: |
| description: Interrupt source of the parent interrupt controller on |
| secondary GICs, or VGIC maintenance interrupt on primary GIC (see |
| below). |
| maxItems: 1 |
| |
| cpu-offset: |
| description: per-cpu offset within the distributor and cpu interface |
| regions, used when the GIC doesn't have banked registers. The offset |
| is cpu-offset * cpu-nr. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| |
| clocks: |
| minItems: 1 |
| maxItems: 2 |
| |
| clock-names: |
| description: List of names for the GIC clock input(s). Valid clock names |
| depend on the GIC variant. |
| oneOf: |
| - const: ic_clk # for "arm,arm11mp-gic" |
| - const: PERIPHCLKEN # for "arm,cortex-a15-gic" |
| - items: # for "arm,cortex-a9-gic" |
| - const: PERIPHCLK |
| - const: PERIPHCLKEN |
| - const: clk # for "arm,gic-400" and "nvidia,tegra210" |
| - const: gclk #for "arm,pl390" |
| |
| power-domains: |
| maxItems: 1 |
| |
| resets: |
| maxItems: 1 |
| |
| required: |
| - compatible |
| - reg |
| |
| patternProperties: |
| "^v2m@[0-9a-f]+$": |
| type: object |
| description: | |
| * GICv2m extension for MSI/MSI-x support (Optional) |
| |
| Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s). |
| This is enabled by specifying v2m sub-node(s). |
| |
| properties: |
| compatible: |
| const: arm,gic-v2m-frame |
| |
| msi-controller: true |
| |
| reg: |
| maxItems: 1 |
| description: GICv2m MSI interface register base and size |
| |
| arm,msi-base-spi: |
| description: When the MSI_TYPER register contains an incorrect value, |
| this property should contain the SPI base of the MSI frame, overriding |
| the HW value. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| |
| arm,msi-num-spis: |
| description: When the MSI_TYPER register contains an incorrect value, |
| this property should contain the number of SPIs assigned to the |
| frame, overriding the HW value. |
| $ref: /schemas/types.yaml#/definitions/uint32 |
| |
| required: |
| - compatible |
| - msi-controller |
| - reg |
| |
| additionalProperties: false |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| // GICv1 |
| intc: interrupt-controller@fff11000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| interrupt-controller; |
| reg = <0xfff11000 0x1000>, |
| <0xfff10100 0x100>; |
| }; |
| |
| - | |
| // GICv2 |
| interrupt-controller@2c001000 { |
| compatible = "arm,cortex-a15-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x2c001000 0x1000>, |
| <0x2c002000 0x2000>, |
| <0x2c004000 0x2000>, |
| <0x2c006000 0x2000>; |
| interrupts = <1 9 0xf04>; |
| }; |
| |
| - | |
| // GICv2m extension for MSI/MSI-x support |
| interrupt-controller@e1101000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| interrupt-controller; |
| interrupts = <1 8 0xf04>; |
| ranges = <0 0xe1100000 0x100000>; |
| reg = <0xe1110000 0x01000>, |
| <0xe112f000 0x02000>, |
| <0xe1140000 0x10000>, |
| <0xe1160000 0x10000>; |
| |
| v2m0: v2m@80000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x80000 0x1000>; |
| }; |
| |
| //... |
| |
| v2mN: v2m@90000 { |
| compatible = "arm,gic-v2m-frame"; |
| msi-controller; |
| reg = <0x90000 0x1000>; |
| }; |
| }; |
| ... |
