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android-kvm / linux / 8b9a02280ebe209ae14fc478b0285745544a257c / . / drivers / gpu / drm / amd / include / navi10_enum.h
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/*
* Copyright (C) 2019 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if !defined (_navi10_ENUM_HEADER)
#define _navi10_ENUM_HEADER
#ifndef _DRIVER_BUILD
#ifndef GL_ZERO
#define GL__ZERO BLEND_ZERO
#define GL__ONE BLEND_ONE
#define GL__SRC_COLOR BLEND_SRC_COLOR
#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
#define GL__DST_COLOR BLEND_DST_COLOR
#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
#define GL__SRC_ALPHA BLEND_SRC_ALPHA
#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
#define GL__DST_ALPHA BLEND_DST_ALPHA
#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
#endif
#endif
/*******************************************************
* GDS DATA_TYPE Enums
*******************************************************/
#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
#define ENUMS_GDS_PERFCOUNT_SELECT_H
typedef enum GDS_PERFCOUNT_SELECT {
GDS_PERF_SEL_DS_ADDR_CONFL = 0,
GDS_PERF_SEL_DS_BANK_CONFL = 1,
GDS_PERF_SEL_WBUF_FLUSH = 2,
GDS_PERF_SEL_WR_COMP = 3,
GDS_PERF_SEL_WBUF_WR = 4,
GDS_PERF_SEL_RBUF_HIT = 5,
GDS_PERF_SEL_RBUF_MISS = 6,
GDS_PERF_SEL_SE0_SH0_NORET = 7,
GDS_PERF_SEL_SE0_SH0_RET = 8,
GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
GDS_PERF_SEL_SE0_SH1_NORET = 21,
GDS_PERF_SEL_SE0_SH1_RET = 22,
GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
GDS_PERF_SEL_SE1_SH0_NORET = 35,
GDS_PERF_SEL_SE1_SH0_RET = 36,
GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
GDS_PERF_SEL_SE1_SH1_NORET = 49,
GDS_PERF_SEL_SE1_SH1_RET = 50,
GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
GDS_PERF_SEL_SE2_SH0_NORET = 63,
GDS_PERF_SEL_SE2_SH0_RET = 64,
GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
GDS_PERF_SEL_SE2_SH1_NORET = 77,
GDS_PERF_SEL_SE2_SH1_RET = 78,
GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
GDS_PERF_SEL_SE3_SH0_NORET = 91,
GDS_PERF_SEL_SE3_SH0_RET = 92,
GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
GDS_PERF_SEL_SE3_SH1_NORET = 105,
GDS_PERF_SEL_SE3_SH1_RET = 106,
GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
GDS_PERF_SEL_GWS_RELEASED = 119,
GDS_PERF_SEL_GWS_BYPASS = 120,
} GDS_PERFCOUNT_SELECT;
#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
/*******************************************************
* Chip Enums
*******************************************************/
/*
* GATCL1RequestType enum
*/
typedef enum GATCL1RequestType {
GATCL1_TYPE_NORMAL = 0x00000000,
GATCL1_TYPE_SHOOTDOWN = 0x00000001,
GATCL1_TYPE_BYPASS = 0x00000002,
} GATCL1RequestType;
/*
* UTCL1RequestType enum
*/
typedef enum UTCL1RequestType {
UTCL1_TYPE_NORMAL = 0x00000000,
UTCL1_TYPE_SHOOTDOWN = 0x00000001,
UTCL1_TYPE_BYPASS = 0x00000002,
} UTCL1RequestType;
/*
* UTCL1FaultType enum
*/
typedef enum UTCL1FaultType {
UTCL1_XNACK_SUCCESS = 0x00000000,
UTCL1_XNACK_RETRY = 0x00000001,
UTCL1_XNACK_PRT = 0x00000002,
UTCL1_XNACK_NO_RETRY = 0x00000003,
} UTCL1FaultType;
/*
* UTCL0RequestType enum
*/
typedef enum UTCL0RequestType {
UTCL0_TYPE_NORMAL = 0x00000000,
UTCL0_TYPE_SHOOTDOWN = 0x00000001,
UTCL0_TYPE_BYPASS = 0x00000002,
} UTCL0RequestType;
/*
* UTCL0FaultType enum
*/
typedef enum UTCL0FaultType {
UTCL0_XNACK_SUCCESS = 0x00000000,
UTCL0_XNACK_RETRY = 0x00000001,
UTCL0_XNACK_PRT = 0x00000002,
UTCL0_XNACK_NO_RETRY = 0x00000003,
} UTCL0FaultType;
/*
* VMEMCMD_RETURN_ORDER enum
*/
typedef enum VMEMCMD_RETURN_ORDER {
VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000,
VMEMCMD_RETURN_IN_ORDER = 0x00000001,
VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002,
} VMEMCMD_RETURN_ORDER;
/*
* GL0V_CACHE_POLICIES enum
*/
typedef enum GL0V_CACHE_POLICIES {
GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
} GL0V_CACHE_POLICIES;
/*
* GL1_CACHE_POLICIES enum
*/
typedef enum GL1_CACHE_POLICIES {
GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
} GL1_CACHE_POLICIES;
/*
* GL1_CACHE_STORE_POLICIES enum
*/
typedef enum GL1_CACHE_STORE_POLICIES {
GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
} GL1_CACHE_STORE_POLICIES;
/*
* TCC_CACHE_POLICIES enum
*/
typedef enum TCC_CACHE_POLICIES {
TCC_CACHE_POLICY_LRU = 0x00000000,
TCC_CACHE_POLICY_STREAM = 0x00000001,
} TCC_CACHE_POLICIES;
/*
* TCC_MTYPE enum
*/
typedef enum TCC_MTYPE {
MTYPE_NC = 0x00000000,
MTYPE_WC = 0x00000001,
MTYPE_CC = 0x00000002,
} TCC_MTYPE;
/*
* GL2_CACHE_POLICIES enum
*/
typedef enum GL2_CACHE_POLICIES {
GL2_CACHE_POLICY_LRU = 0x00000000,
GL2_CACHE_POLICY_STREAM = 0x00000001,
GL2_CACHE_POLICY_NOA = 0x00000002,
GL2_CACHE_POLICY_BYPASS = 0x00000003,
} GL2_CACHE_POLICIES;
/*
* MTYPE enum
*/
typedef enum MTYPE {
MTYPE_C_RW_US = 0x00000000,
MTYPE_RESERVED_1 = 0x00000001,
MTYPE_C_RO_S = 0x00000002,
MTYPE_UC = 0x00000003,
MTYPE_C_RW_S = 0x00000004,
MTYPE_RESERVED_5 = 0x00000005,
MTYPE_C_RO_US = 0x00000006,
MTYPE_RESERVED_7 = 0x00000007,
} MTYPE;
/*
* RMI_CID enum
*/
typedef enum RMI_CID {
RMI_CID_CC = 0x00000000,
RMI_CID_FC = 0x00000001,
RMI_CID_CM = 0x00000002,
RMI_CID_DC = 0x00000003,
RMI_CID_Z = 0x00000004,
RMI_CID_S = 0x00000005,
RMI_CID_TILE = 0x00000006,
RMI_CID_ZPCPSD = 0x00000007,
} RMI_CID;
/*
* WritePolicy enum
*/
typedef enum WritePolicy {
CACHE_LRU_WR = 0x00000000,
CACHE_STREAM = 0x00000001,
CACHE_BYPASS = 0x00000002,
UNCACHED_WR = 0x00000003,
} WritePolicy;
/*
* ReadPolicy enum
*/
typedef enum ReadPolicy {
CACHE_LRU_RD = 0x00000000,
CACHE_NOA = 0x00000001,
UNCACHED_RD = 0x00000002,
RESERVED_RDPOLICY = 0x00000003,
} ReadPolicy;
/*
* PERFMON_COUNTER_MODE enum
*/
typedef enum PERFMON_COUNTER_MODE {
PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
PERFMON_COUNTER_MODE_MAX = 0x00000002,
PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
} PERFMON_COUNTER_MODE;
/*
* PERFMON_SPM_MODE enum
*/
typedef enum PERFMON_SPM_MODE {
PERFMON_SPM_MODE_OFF = 0x00000000,
PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
} PERFMON_SPM_MODE;
/*
* SurfaceTiling enum
*/
typedef enum SurfaceTiling {
ARRAY_LINEAR = 0x00000000,
ARRAY_TILED = 0x00000001,
} SurfaceTiling;
/*
* SurfaceArray enum
*/
typedef enum SurfaceArray {
ARRAY_1D = 0x00000000,
ARRAY_2D = 0x00000001,
ARRAY_3D = 0x00000002,
ARRAY_3D_SLICE = 0x00000003,
} SurfaceArray;
/*
* ColorArray enum
*/
typedef enum ColorArray {
ARRAY_2D_ALT_COLOR = 0x00000000,
ARRAY_2D_COLOR = 0x00000001,
ARRAY_3D_SLICE_COLOR = 0x00000003,
} ColorArray;
/*
* DepthArray enum
*/
typedef enum DepthArray {
ARRAY_2D_ALT_DEPTH = 0x00000000,
ARRAY_2D_DEPTH = 0x00000001,
} DepthArray;
/*
* ENUM_NUM_SIMD_PER_CU enum
*/
typedef enum ENUM_NUM_SIMD_PER_CU {
NUM_SIMD_PER_CU = 0x00000002,
} ENUM_NUM_SIMD_PER_CU;
/*
* DSM_ENABLE_ERROR_INJECT enum
*/
typedef enum DSM_ENABLE_ERROR_INJECT {
DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
} DSM_ENABLE_ERROR_INJECT;
/*
* DSM_SELECT_INJECT_DELAY enum
*/
typedef enum DSM_SELECT_INJECT_DELAY {
DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
} DSM_SELECT_INJECT_DELAY;
/*
* DSM_DATA_SEL enum
*/
typedef enum DSM_DATA_SEL {
DSM_DATA_SEL_DISABLE = 0x00000000,
DSM_DATA_SEL_0 = 0x00000001,
DSM_DATA_SEL_1 = 0x00000002,
DSM_DATA_SEL_BOTH = 0x00000003,
} DSM_DATA_SEL;
/*
* DSM_SINGLE_WRITE enum
*/
typedef enum DSM_SINGLE_WRITE {
DSM_SINGLE_WRITE_DIS = 0x00000000,
DSM_SINGLE_WRITE_EN = 0x00000001,
} DSM_SINGLE_WRITE;
/*
* Hdp_SurfaceEndian enum
*/
typedef enum Hdp_SurfaceEndian {
HDP_ENDIAN_NONE = 0x00000000,
HDP_ENDIAN_8IN16 = 0x00000001,
HDP_ENDIAN_8IN32 = 0x00000002,
HDP_ENDIAN_8IN64 = 0x00000003,
} Hdp_SurfaceEndian;
/*******************************************************
* CNVC_CFG Enums
*******************************************************/
/*
* CNVC_ENABLE enum
*/
typedef enum CNVC_ENABLE {
CNVC_DIS = 0x00000000,
CNVC_EN = 0x00000001,
} CNVC_ENABLE;
/*
* CNVC_BYPASS enum
*/
typedef enum CNVC_BYPASS {
CNVC_BYPASS_DISABLE = 0x00000000,
CNVC_BYPASS_EN = 0x00000001,
} CNVC_BYPASS;
/*
* CNVC_PENDING enum
*/
typedef enum CNVC_PENDING {
CNVC_NOT_PENDING = 0x00000000,
CNVC_YES_PENDING = 0x00000001,
} CNVC_PENDING;
/*
* DENORM_TRUNCATE enum
*/
typedef enum DENORM_TRUNCATE {
CNVC_ROUND = 0x00000000,
CNVC_TRUNCATE = 0x00000001,
} DENORM_TRUNCATE;
/*
* PIX_EXPAND_MODE enum
*/
typedef enum PIX_EXPAND_MODE {
PIX_DYNAMIC_EXPANSION = 0x00000000,
PIX_ZERO_EXPANSION = 0x00000001,
} PIX_EXPAND_MODE;
/*
* SURFACE_PIXEL_FORMAT enum
*/
typedef enum SURFACE_PIXEL_FORMAT {
ARGB1555 = 0x00000001,
RGBA5551 = 0x00000002,
RGB565 = 0x00000003,
BGR565 = 0x00000004,
ARGB4444 = 0x00000005,
RGBA4444 = 0x00000006,
ARGB8888 = 0x00000008,
RGBA8888 = 0x00000009,
ARGB2101010 = 0x0000000a,
RGBA1010102 = 0x0000000b,
AYCrCb8888 = 0x0000000c,
YCrCbA8888 = 0x0000000d,
ACrYCb8888 = 0x0000000e,
CrYCbA8888 = 0x0000000f,
ARGB16161616_10MSB = 0x00000010,
RGBA16161616_10MSB = 0x00000011,
ARGB16161616_10LSB = 0x00000012,
RGBA16161616_10LSB = 0x00000013,
ARGB16161616_12MSB = 0x00000014,
RGBA16161616_12MSB = 0x00000015,
ARGB16161616_12LSB = 0x00000016,
RGBA16161616_12LSB = 0x00000017,
ARGB16161616_FLOAT = 0x00000018,
RGBA16161616_FLOAT = 0x00000019,
ARGB16161616_UNORM = 0x0000001a,
RGBA16161616_UNORM = 0x0000001b,
ARGB16161616_SNORM = 0x0000001c,
RGBA16161616_SNORM = 0x0000001d,
AYCrCb16161616_10MSB = 0x00000020,
AYCrCb16161616_10LSB = 0x00000021,
YCrCbA16161616_10MSB = 0x00000022,
YCrCbA16161616_10LSB = 0x00000023,
ACrYCb16161616_10MSB = 0x00000024,
ACrYCb16161616_10LSB = 0x00000025,
CrYCbA16161616_10MSB = 0x00000026,
CrYCbA16161616_10LSB = 0x00000027,
AYCrCb16161616_12MSB = 0x00000028,
AYCrCb16161616_12LSB = 0x00000029,
YCrCbA16161616_12MSB = 0x0000002a,
YCrCbA16161616_12LSB = 0x0000002b,
ACrYCb16161616_12MSB = 0x0000002c,
ACrYCb16161616_12LSB = 0x0000002d,
CrYCbA16161616_12MSB = 0x0000002e,
CrYCbA16161616_12LSB = 0x0000002f,
Y8_CrCb88_420_PLANAR = 0x00000040,
Y8_CbCr88_420_PLANAR = 0x00000041,
Y10_CrCb1010_420_PLANAR = 0x00000042,
Y10_CbCr1010_420_PLANAR = 0x00000043,
Y12_CrCb1212_420_PLANAR = 0x00000044,
Y12_CbCr1212_420_PLANAR = 0x00000045,
YCrYCb8888_422_PACKED = 0x00000048,
YCbYCr8888_422_PACKED = 0x00000049,
CrYCbY8888_422_PACKED = 0x0000004a,
CbYCrY8888_422_PACKED = 0x0000004b,
YCrYCb10101010_422_PACKED = 0x0000004c,
YCbYCr10101010_422_PACKED = 0x0000004d,
CrYCbY10101010_422_PACKED = 0x0000004e,
CbYCrY10101010_422_PACKED = 0x0000004f,
YCrYCb12121212_422_PACKED = 0x00000050,
YCbYCr12121212_422_PACKED = 0x00000051,
CrYCbY12121212_422_PACKED = 0x00000052,
CbYCrY12121212_422_PACKED = 0x00000053,
RGB111110_FIX = 0x00000070,
BGR101111_FIX = 0x00000071,
ACrYCb2101010 = 0x00000072,
CrYCbA1010102 = 0x00000073,
RGB111110_FLOAT = 0x00000076,
BGR101111_FLOAT = 0x00000077,
MONO_8 = 0x00000078,
MONO_10MSB = 0x00000079,
MONO_10LSB = 0x0000007a,
MONO_12MSB = 0x0000007b,
MONO_12LSB = 0x0000007c,
MONO_16 = 0x0000007d,
} SURFACE_PIXEL_FORMAT;
/*
* XNORM enum
*/
typedef enum XNORM {
XNORM_A = 0x00000000,
XNORM_B = 0x00000001,
} XNORM;
/*
* COLOR_KEYER_MODE enum
*/
typedef enum COLOR_KEYER_MODE {
FORCE_00 = 0x00000000,
FORCE_FF = 0x00000001,
RANGE_00 = 0x00000002,
RANGE_FF = 0x00000003,
} COLOR_KEYER_MODE;
/*******************************************************
* CNVC_CUR Enums
*******************************************************/
/*
* CUR_ENABLE enum
*/
typedef enum CUR_ENABLE {
CUR_DIS = 0x00000000,
CUR_EN = 0x00000001,
} CUR_ENABLE;
/*
* CUR_PENDING enum
*/
typedef enum CUR_PENDING {
CUR_NOT_PENDING = 0x00000000,
CUR_YES_PENDING = 0x00000001,
} CUR_PENDING;
/*
* CUR_EXPAND_MODE enum
*/
typedef enum CUR_EXPAND_MODE {
CUR_DYNAMIC_EXPANSION = 0x00000000,
CUR_ZERO_EXPANSION = 0x00000001,
} CUR_EXPAND_MODE;
/*
* CUR_ROM_EN enum
*/
typedef enum CUR_ROM_EN {
CUR_FP_NO_ROM = 0x00000000,
CUR_FP_USE_ROM = 0x00000001,
} CUR_ROM_EN;
/*
* CUR_MODE enum
*/
typedef enum CUR_MODE {
MONO_2BIT = 0x00000000,
COLOR_24BIT_1BIT_AND = 0x00000001,
COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
COLOR_64BIT_FP_PREMULT = 0x00000004,
COLOR_64BIT_FP_UNPREMULT = 0x00000005,
} CUR_MODE;
/*
* CUR_INV_CLAMP enum
*/
typedef enum CUR_INV_CLAMP {
CUR_CLAMP_DIS = 0x00000000,
CUR_CLAMP_EN = 0x00000001,
} CUR_INV_CLAMP;
/*******************************************************
* DSCL Enums
*******************************************************/
/*
* SCL_COEF_FILTER_TYPE_SEL enum
*/
typedef enum SCL_COEF_FILTER_TYPE_SEL {
SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
SCL_COEF_ALPHA_VERT_FILTER = 0x00000004,
SCL_COEF_ALPHA_HORZ_FILTER = 0x00000005,
} SCL_COEF_FILTER_TYPE_SEL;
/*
* DSCL_MODE_SEL enum
*/
typedef enum DSCL_MODE_SEL {
DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
DSCL_MODE_DSCL_BYPASS = 0x00000006,
} DSCL_MODE_SEL;
/*
* SCL_AUTOCAL_MODE enum
*/
typedef enum SCL_AUTOCAL_MODE {
AUTOCAL_MODE_OFF = 0x00000000,
AUTOCAL_MODE_AUTOSCALE = 0x00000001,
AUTOCAL_MODE_AUTOCENTER = 0x00000002,
AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
} SCL_AUTOCAL_MODE;
/*
* SCL_COEF_RAM_SEL enum
*/
typedef enum SCL_COEF_RAM_SEL {
SCL_COEF_RAM_SEL_0 = 0x00000000,
SCL_COEF_RAM_SEL_1 = 0x00000001,
} SCL_COEF_RAM_SEL;
/*
* SCL_CHROMA_COEF enum
*/
typedef enum SCL_CHROMA_COEF {
SCL_CHROMA_COEF_LUMA = 0x00000000,
SCL_CHROMA_COEF_CHROMA = 0x00000001,
} SCL_CHROMA_COEF;
/*
* SCL_ALPHA_COEF enum
*/
typedef enum SCL_ALPHA_COEF {
SCL_ALPHA_COEF_LUMA = 0x00000000,
SCL_ALPHA_COEF_ALPHA = 0x00000001,
} SCL_ALPHA_COEF;
/*
* COEF_RAM_SELECT_RD enum
*/
typedef enum COEF_RAM_SELECT_RD {
COEF_RAM_SELECT_BACK = 0x00000000,
COEF_RAM_SELECT_CURRENT = 0x00000001,
} COEF_RAM_SELECT_RD;
/*
* SCL_2TAP_HARDCODE enum
*/
typedef enum SCL_2TAP_HARDCODE {
SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
} SCL_2TAP_HARDCODE;
/*
* SCL_SHARP_EN enum
*/
typedef enum SCL_SHARP_EN {
SCL_SHARP_DISABLE = 0x00000000,
SCL_SHARP_ENABLE = 0x00000001,
} SCL_SHARP_EN;
/*
* SCL_BOUNDARY enum
*/
typedef enum SCL_BOUNDARY {
SCL_BOUNDARY_EDGE = 0x00000000,
SCL_BOUNDARY_BLACK = 0x00000001,
} SCL_BOUNDARY;
/*
* LB_INTERLEAVE_EN enum
*/
typedef enum LB_INTERLEAVE_EN {
LB_INTERLEAVE_DISABLE = 0x00000000,
LB_INTERLEAVE_ENABLE = 0x00000001,
} LB_INTERLEAVE_EN;
/*
* LB_ALPHA_EN enum
*/
typedef enum LB_ALPHA_EN {
LB_ALPHA_DISABLE = 0x00000000,
LB_ALPHA_ENABLE = 0x00000001,
} LB_ALPHA_EN;
/*
* OBUF_BYPASS_SEL enum
*/
typedef enum OBUF_BYPASS_SEL {
OBUF_BYPASS_DIS = 0x00000000,
OBUF_BYPASS_EN = 0x00000001,
} OBUF_BYPASS_SEL;
/*
* OBUF_USE_FULL_BUFFER_SEL enum
*/
typedef enum OBUF_USE_FULL_BUFFER_SEL {
OBUF_RECOUT = 0x00000000,
OBUF_FULL = 0x00000001,
} OBUF_USE_FULL_BUFFER_SEL;
/*
* OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
*/
typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
OBUF_FULL_RECOUT = 0x00000000,
OBUF_HALF_RECOUT = 0x00000001,
} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
/*******************************************************
* CM Enums
*******************************************************/
/*
* CM_BYPASS enum
*/
typedef enum CM_BYPASS {
NON_BYPASS = 0x00000000,
BYPASS_EN = 0x00000001,
} CM_BYPASS;
/*
* CM_EN enum
*/
typedef enum CM_EN {
CM_DISABLE = 0x00000000,
CM_ENABLE = 0x00000001,
} CM_EN;
/*
* CM_PENDING enum
*/
typedef enum CM_PENDING {
CM_NOT_PENDING = 0x00000000,
CM_YES_PENDING = 0x00000001,
} CM_PENDING;
/*
* CM_DATA_SIGNED enum
*/
typedef enum CM_DATA_SIGNED {
UNSIGNED = 0x00000000,
SIGNED = 0x00000001,
} CM_DATA_SIGNED;
/*
* CM_WRITE_BASE_ONLY enum
*/
typedef enum CM_WRITE_BASE_ONLY {
WRITE_BOTH = 0x00000000,
WRITE_BASE_ONLY = 0x00000001,
} CM_WRITE_BASE_ONLY;
/*
* CM_LUT_4_CONFIG_ENUM enum
*/
typedef enum CM_LUT_4_CONFIG_ENUM {
LUT_4CFG_NO_MEMORY = 0x00000000,
LUT_4CFG_ROM_A = 0x00000001,
LUT_4CFG_ROM_B = 0x00000002,
LUT_4CFG_MEMORY_A = 0x00000003,
LUT_4CFG_MEMORY_B = 0x00000004,
} CM_LUT_4_CONFIG_ENUM;
/*
* CM_LUT_2_CONFIG_ENUM enum
*/
typedef enum CM_LUT_2_CONFIG_ENUM {
LUT_2CFG_NO_MEMORY = 0x00000000,
LUT_2CFG_MEMORY_A = 0x00000001,
LUT_2CFG_MEMORY_B = 0x00000002,
} CM_LUT_2_CONFIG_ENUM;
/*
* CM_LUT_4_MODE_ENUM enum
*/
typedef enum CM_LUT_4_MODE_ENUM {
LUT_4_MODE_BYPASS = 0x00000000,
LUT_4_MODE_ROMA_LUT = 0x00000001,
LUT_4_MODE_ROMB_LUT = 0x00000002,
LUT_4_MODE_RAMA_LUT = 0x00000003,
LUT_4_MODE_RAMB_LUT = 0x00000004,
} CM_LUT_4_MODE_ENUM;
/*
* CM_LUT_2_MODE_ENUM enum
*/
typedef enum CM_LUT_2_MODE_ENUM {
LUT_2_MODE_BYPASS = 0x00000000,
LUT_2_MODE_RAMA_LUT = 0x00000001,
LUT_2_MODE_RAMB_LUT = 0x00000002,
} CM_LUT_2_MODE_ENUM;
/*
* CM_LUT_RAM_SEL enum
*/
typedef enum CM_LUT_RAM_SEL {
RAMA_ACCESS = 0x00000000,
RAMB_ACCESS = 0x00000001,
} CM_LUT_RAM_SEL;
/*
* CM_LUT_NUM_SEG enum
*/
typedef enum CM_LUT_NUM_SEG {
SEGMENTS_1 = 0x00000000,
SEGMENTS_2 = 0x00000001,
SEGMENTS_4 = 0x00000002,
SEGMENTS_8 = 0x00000003,
SEGMENTS_16 = 0x00000004,
SEGMENTS_32 = 0x00000005,
SEGMENTS_64 = 0x00000006,
SEGMENTS_128 = 0x00000007,
} CM_LUT_NUM_SEG;
/*
* CM_ICSC_MODE_ENUM enum
*/
typedef enum CM_ICSC_MODE_ENUM {
BYPASS_ICSC = 0x00000000,
COEF_ICSC = 0x00000001,
COEF_ICSC_B = 0x00000002,
} CM_ICSC_MODE_ENUM;
/*
* CM_GAMUT_REMAP_MODE_ENUM enum
*/
typedef enum CM_GAMUT_REMAP_MODE_ENUM {
BYPASS_GAMUT = 0x00000000,
GAMUT_COEF = 0x00000001,
GAMUT_COEF_B = 0x00000002,
} CM_GAMUT_REMAP_MODE_ENUM;
/*
* CM_COEF_FORMAT_ENUM enum
*/
typedef enum CM_COEF_FORMAT_ENUM {
FIX_S2_13 = 0x00000000,
FIX_S3_12 = 0x00000001,
} CM_COEF_FORMAT_ENUM;
/*
* CMC_LUT_2_CONFIG_ENUM enum
*/
typedef enum CMC_LUT_2_CONFIG_ENUM {
CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
CMC_LUT_2CFG_MEMORY_A = 0x00000001,
CMC_LUT_2CFG_MEMORY_B = 0x00000002,
} CMC_LUT_2_CONFIG_ENUM;
/*
* CMC_LUT_2_MODE_ENUM enum
*/
typedef enum CMC_LUT_2_MODE_ENUM {
CMC_LUT_2_MODE_BYPASS = 0x00000000,
CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
} CMC_LUT_2_MODE_ENUM;
/*
* CMC_LUT_RAM_SEL enum
*/
typedef enum CMC_LUT_RAM_SEL {
CMC_RAMA_ACCESS = 0x00000000,
CMC_RAMB_ACCESS = 0x00000001,
} CMC_LUT_RAM_SEL;
/*
* CMC_3DLUT_RAM_SEL enum
*/
typedef enum CMC_3DLUT_RAM_SEL {
CMC_RAM0_ACCESS = 0x00000000,
CMC_RAM1_ACCESS = 0x00000001,
CMC_RAM2_ACCESS = 0x00000002,
CMC_RAM3_ACCESS = 0x00000003,
} CMC_3DLUT_RAM_SEL;
/*
* CMC_LUT_NUM_SEG enum
*/
typedef enum CMC_LUT_NUM_SEG {
CMC_SEGMENTS_1 = 0x00000000,
CMC_SEGMENTS_2 = 0x00000001,
CMC_SEGMENTS_4 = 0x00000002,
CMC_SEGMENTS_8 = 0x00000003,
CMC_SEGMENTS_16 = 0x00000004,
CMC_SEGMENTS_32 = 0x00000005,
CMC_SEGMENTS_64 = 0x00000006,
CMC_SEGMENTS_128 = 0x00000007,
} CMC_LUT_NUM_SEG;
/*
* CMC_3DLUT_30BIT_ENUM enum
*/
typedef enum CMC_3DLUT_30BIT_ENUM {
CMC_3DLUT_36BIT = 0x00000000,
CMC_3DLUT_30BIT = 0x00000001,
} CMC_3DLUT_30BIT_ENUM;
/*
* CMC_3DLUT_SIZE_ENUM enum
*/
typedef enum CMC_3DLUT_SIZE_ENUM {
CMC_3DLUT_17CUBE = 0x00000000,
CMC_3DLUT_9CUBE = 0x00000001,
} CMC_3DLUT_SIZE_ENUM;
/*******************************************************
* DPP_TOP Enums
*******************************************************/
/*
* TEST_CLK_SEL enum
*/
typedef enum TEST_CLK_SEL {
TEST_CLK_SEL_0 = 0x00000000,
TEST_CLK_SEL_1 = 0x00000001,
TEST_CLK_SEL_2 = 0x00000002,
TEST_CLK_SEL_3 = 0x00000003,
TEST_CLK_SEL_4 = 0x00000004,
TEST_CLK_SEL_5 = 0x00000005,
TEST_CLK_SEL_6 = 0x00000006,
TEST_CLK_SEL_7 = 0x00000007,
TEST_CLK_SEL_8 = 0x00000008,
} TEST_CLK_SEL;
/*
* CRC_SRC_SEL enum
*/
typedef enum CRC_SRC_SEL {
CRC_SRC_0 = 0x00000000,
CRC_SRC_1 = 0x00000001,
CRC_SRC_2 = 0x00000002,
CRC_SRC_3 = 0x00000003,
} CRC_SRC_SEL;
/*
* CRC_IN_PIX_SEL enum
*/
typedef enum CRC_IN_PIX_SEL {
CRC_IN_PIX_0 = 0x00000000,
CRC_IN_PIX_1 = 0x00000001,
CRC_IN_PIX_2 = 0x00000002,
CRC_IN_PIX_3 = 0x00000003,
CRC_IN_PIX_4 = 0x00000004,
CRC_IN_PIX_5 = 0x00000005,
CRC_IN_PIX_6 = 0x00000006,
CRC_IN_PIX_7 = 0x00000007,
} CRC_IN_PIX_SEL;
/*
* CRC_CUR_BITS_SEL enum
*/
typedef enum CRC_CUR_BITS_SEL {
CRC_CUR_BITS_0 = 0x00000000,
CRC_CUR_BITS_1 = 0x00000001,
} CRC_CUR_BITS_SEL;
/*
* CRC_IN_CUR_SEL enum
*/
typedef enum CRC_IN_CUR_SEL {
CRC_IN_CUR_0 = 0x00000000,
CRC_IN_CUR_1 = 0x00000001,
} CRC_IN_CUR_SEL;
/*
* CRC_CUR_SEL enum
*/
typedef enum CRC_CUR_SEL {
CRC_CUR_0 = 0x00000000,
CRC_CUR_1 = 0x00000001,
} CRC_CUR_SEL;
/*
* CRC_STEREO_SEL enum
*/
typedef enum CRC_STEREO_SEL {
CRC_STEREO_0 = 0x00000000,
CRC_STEREO_1 = 0x00000001,
CRC_STEREO_2 = 0x00000002,
CRC_STEREO_3 = 0x00000003,
} CRC_STEREO_SEL;
/*
* CRC_INTERLACE_SEL enum
*/
typedef enum CRC_INTERLACE_SEL {
CRC_INTERLACE_0 = 0x00000000,
CRC_INTERLACE_1 = 0x00000001,
CRC_INTERLACE_2 = 0x00000002,
CRC_INTERLACE_3 = 0x00000003,
} CRC_INTERLACE_SEL;
/*******************************************************
* DC_PERFMON Enums
*******************************************************/
/*
* PERFCOUNTER_CVALUE_SEL enum
*/
typedef enum PERFCOUNTER_CVALUE_SEL {
PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
} PERFCOUNTER_CVALUE_SEL;
/*
* PERFCOUNTER_INC_MODE enum
*/
typedef enum PERFCOUNTER_INC_MODE {
PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
PERFCOUNTER_INC_MODE_LSB = 0x00000002,
PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
} PERFCOUNTER_INC_MODE;
/*
* PERFCOUNTER_HW_CNTL_SEL enum
*/
typedef enum PERFCOUNTER_HW_CNTL_SEL {
PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
} PERFCOUNTER_HW_CNTL_SEL;
/*
* PERFCOUNTER_RUNEN_MODE enum
*/
typedef enum PERFCOUNTER_RUNEN_MODE {
PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
} PERFCOUNTER_RUNEN_MODE;
/*
* PERFCOUNTER_CNTOFF_START_DIS enum
*/
typedef enum PERFCOUNTER_CNTOFF_START_DIS {
PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
} PERFCOUNTER_CNTOFF_START_DIS;
/*
* PERFCOUNTER_RESTART_EN enum
*/
typedef enum PERFCOUNTER_RESTART_EN {
PERFCOUNTER_RESTART_DISABLE = 0x00000000,
PERFCOUNTER_RESTART_ENABLE = 0x00000001,
} PERFCOUNTER_RESTART_EN;
/*
* PERFCOUNTER_INT_EN enum
*/
typedef enum PERFCOUNTER_INT_EN {
PERFCOUNTER_INT_DISABLE = 0x00000000,
PERFCOUNTER_INT_ENABLE = 0x00000001,
} PERFCOUNTER_INT_EN;
/*
* PERFCOUNTER_OFF_MASK enum
*/
typedef enum PERFCOUNTER_OFF_MASK {
PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
} PERFCOUNTER_OFF_MASK;
/*
* PERFCOUNTER_ACTIVE enum
*/
typedef enum PERFCOUNTER_ACTIVE {
PERFCOUNTER_IS_IDLE = 0x00000000,
PERFCOUNTER_IS_ACTIVE = 0x00000001,
} PERFCOUNTER_ACTIVE;
/*
* PERFCOUNTER_INT_TYPE enum
*/
typedef enum PERFCOUNTER_INT_TYPE {
PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
} PERFCOUNTER_INT_TYPE;
/*
* PERFCOUNTER_COUNTED_VALUE_TYPE enum
*/
typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
} PERFCOUNTER_COUNTED_VALUE_TYPE;
/*
* PERFCOUNTER_HW_STOP1_SEL enum
*/
typedef enum PERFCOUNTER_HW_STOP1_SEL {
PERFCOUNTER_HW_STOP1_0 = 0x00000000,
PERFCOUNTER_HW_STOP1_1 = 0x00000001,
} PERFCOUNTER_HW_STOP1_SEL;
/*
* PERFCOUNTER_HW_STOP2_SEL enum
*/
typedef enum PERFCOUNTER_HW_STOP2_SEL {
PERFCOUNTER_HW_STOP2_0 = 0x00000000,
PERFCOUNTER_HW_STOP2_1 = 0x00000001,
} PERFCOUNTER_HW_STOP2_SEL;
/*
* PERFCOUNTER_CNTL_SEL enum
*/
typedef enum PERFCOUNTER_CNTL_SEL {
PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
} PERFCOUNTER_CNTL_SEL;
/*
* PERFCOUNTER_CNT0_STATE enum
*/
typedef enum PERFCOUNTER_CNT0_STATE {
PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT0_STATE_START = 0x00000001,
PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT0_STATE;
/*
* PERFCOUNTER_STATE_SEL0 enum
*/
typedef enum PERFCOUNTER_STATE_SEL0 {
PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL0;
/*
* PERFCOUNTER_CNT1_STATE enum
*/
typedef enum PERFCOUNTER_CNT1_STATE {
PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT1_STATE_START = 0x00000001,
PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT1_STATE;
/*
* PERFCOUNTER_STATE_SEL1 enum
*/
typedef enum PERFCOUNTER_STATE_SEL1 {
PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL1;
/*
* PERFCOUNTER_CNT2_STATE enum
*/
typedef enum PERFCOUNTER_CNT2_STATE {
PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT2_STATE_START = 0x00000001,
PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT2_STATE;
/*
* PERFCOUNTER_STATE_SEL2 enum
*/
typedef enum PERFCOUNTER_STATE_SEL2 {
PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL2;
/*
* PERFCOUNTER_CNT3_STATE enum
*/
typedef enum PERFCOUNTER_CNT3_STATE {
PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT3_STATE_START = 0x00000001,
PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT3_STATE;
/*
* PERFCOUNTER_STATE_SEL3 enum
*/
typedef enum PERFCOUNTER_STATE_SEL3 {
PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL3;
/*
* PERFCOUNTER_CNT4_STATE enum
*/
typedef enum PERFCOUNTER_CNT4_STATE {
PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT4_STATE_START = 0x00000001,
PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT4_STATE;
/*
* PERFCOUNTER_STATE_SEL4 enum
*/
typedef enum PERFCOUNTER_STATE_SEL4 {
PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL4;
/*
* PERFCOUNTER_CNT5_STATE enum
*/
typedef enum PERFCOUNTER_CNT5_STATE {
PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT5_STATE_START = 0x00000001,
PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT5_STATE;
/*
* PERFCOUNTER_STATE_SEL5 enum
*/
typedef enum PERFCOUNTER_STATE_SEL5 {
PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL5;
/*
* PERFCOUNTER_CNT6_STATE enum
*/
typedef enum PERFCOUNTER_CNT6_STATE {
PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT6_STATE_START = 0x00000001,
PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT6_STATE;
/*
* PERFCOUNTER_STATE_SEL6 enum
*/
typedef enum PERFCOUNTER_STATE_SEL6 {
PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL6;
/*
* PERFCOUNTER_CNT7_STATE enum
*/
typedef enum PERFCOUNTER_CNT7_STATE {
PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
PERFCOUNTER_CNT7_STATE_START = 0x00000001,
PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
} PERFCOUNTER_CNT7_STATE;
/*
* PERFCOUNTER_STATE_SEL7 enum
*/
typedef enum PERFCOUNTER_STATE_SEL7 {
PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
} PERFCOUNTER_STATE_SEL7;
/*
* PERFMON_STATE enum
*/
typedef enum PERFMON_STATE {
PERFMON_STATE_RESET = 0x00000000,
PERFMON_STATE_START = 0x00000001,
PERFMON_STATE_FREEZE = 0x00000002,
PERFMON_STATE_HW = 0x00000003,
} PERFMON_STATE;
/*
* PERFMON_CNTOFF_AND_OR enum
*/
typedef enum PERFMON_CNTOFF_AND_OR {
PERFMON_CNTOFF_OR = 0x00000000,
PERFMON_CNTOFF_AND = 0x00000001,
} PERFMON_CNTOFF_AND_OR;
/*
* PERFMON_CNTOFF_INT_EN enum
*/
typedef enum PERFMON_CNTOFF_INT_EN {
PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
} PERFMON_CNTOFF_INT_EN;
/*
* PERFMON_CNTOFF_INT_TYPE enum
*/
typedef enum PERFMON_CNTOFF_INT_TYPE {
PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
} PERFMON_CNTOFF_INT_TYPE;
/*******************************************************
* HUBP Enums
*******************************************************/
/*
* ROTATION_ANGLE enum
*/
typedef enum ROTATION_ANGLE {
ROTATE_0_DEGREES = 0x00000000,
ROTATE_90_DEGREES = 0x00000001,
ROTATE_180_DEGREES = 0x00000002,
ROTATE_270_DEGREES = 0x00000003,
} ROTATION_ANGLE;
/*
* H_MIRROR_EN enum
*/
typedef enum H_MIRROR_EN {
HW_MIRRORING_DISABLE = 0x00000000,
HW_MIRRORING_ENABLE = 0x00000001,
} H_MIRROR_EN;
/*
* NUM_PIPES enum
*/
typedef enum NUM_PIPES {
ONE_PIPE = 0x00000000,
TWO_PIPES = 0x00000001,
FOUR_PIPES = 0x00000002,
EIGHT_PIPES = 0x00000003,
SIXTEEN_PIPES = 0x00000004,
THIRTY_TWO_PIPES = 0x00000005,
SIXTY_FOUR_PIPES = 0x00000006,
} NUM_PIPES;
/*
* NUM_BANKS enum
*/
typedef enum NUM_BANKS {
ONE_BANK = 0x00000000,
TWO_BANKS = 0x00000001,
FOUR_BANKS = 0x00000002,
EIGHT_BANKS = 0x00000003,
SIXTEEN_BANKS = 0x00000004,
} NUM_BANKS;
/*
* SW_MODE enum
*/
typedef enum SW_MODE {
SWIZZLE_LINEAR = 0x00000000,
SWIZZLE_4KB_S = 0x00000005,
SWIZZLE_4KB_D = 0x00000006,
SWIZZLE_64KB_S = 0x00000009,
SWIZZLE_64KB_D = 0x0000000a,
SWIZZLE_VAR_S = 0x0000000d,
SWIZZLE_VAR_D = 0x0000000e,
SWIZZLE_64KB_S_T = 0x00000011,
SWIZZLE_64KB_D_T = 0x00000012,
SWIZZLE_4KB_S_X = 0x00000015,
SWIZZLE_4KB_D_X = 0x00000016,
SWIZZLE_64KB_S_X = 0x00000019,
SWIZZLE_64KB_D_X = 0x0000001a,
SWIZZLE_64KB_R_X = 0x0000001b,
SWIZZLE_VAR_S_X = 0x0000001d,
SWIZZLE_VAR_D_X = 0x0000001e,
} SW_MODE;
/*
* PIPE_INTERLEAVE enum
*/
typedef enum PIPE_INTERLEAVE {
PIPE_INTERLEAVE_256B = 0x00000000,
PIPE_INTERLEAVE_512B = 0x00000001,
PIPE_INTERLEAVE_1KB = 0x00000002,
} PIPE_INTERLEAVE;
/*
* LEGACY_PIPE_INTERLEAVE enum
*/
typedef enum LEGACY_PIPE_INTERLEAVE {
LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
} LEGACY_PIPE_INTERLEAVE;
/*
* NUM_SE enum
*/
typedef enum NUM_SE {
ONE_SHADER_ENGIN = 0x00000000,
TWO_SHADER_ENGINS = 0x00000001,
FOUR_SHADER_ENGINS = 0x00000002,
EIGHT_SHADER_ENGINS = 0x00000003,
} NUM_SE;
/*
* NUM_RB_PER_SE enum
*/
typedef enum NUM_RB_PER_SE {
ONE_RB_PER_SE = 0x00000000,
TWO_RB_PER_SE = 0x00000001,
FOUR_RB_PER_SE = 0x00000002,
} NUM_RB_PER_SE;
/*
* MAX_COMPRESSED_FRAGS enum
*/
typedef enum MAX_COMPRESSED_FRAGS {
ONE_FRAGMENT = 0x00000000,
TWO_FRAGMENTS = 0x00000001,
FOUR_FRAGMENTS = 0x00000002,
EIGHT_FRAGMENTS = 0x00000003,
} MAX_COMPRESSED_FRAGS;
/*
* DIM_TYPE enum
*/
typedef enum DIM_TYPE {
DIM_TYPE_1D = 0x00000000,
DIM_TYPE_2D = 0x00000001,
DIM_TYPE_3D = 0x00000002,
DIM_TYPE_RESERVED = 0x00000003,
} DIM_TYPE;
/*
* META_LINEAR enum
*/
typedef enum META_LINEAR {
META_SURF_TILED = 0x00000000,
META_SURF_LINEAR = 0x00000001,
} META_LINEAR;
/*
* RB_ALIGNED enum
*/
typedef enum RB_ALIGNED {
RB_UNALIGNED_META_SURF = 0x00000000,
RB_ALIGNED_META_SURF = 0x00000001,
} RB_ALIGNED;
/*
* PIPE_ALIGNED enum
*/
typedef enum PIPE_ALIGNED {
PIPE_UNALIGNED_SURF = 0x00000000,
PIPE_ALIGNED_SURF = 0x00000001,
} PIPE_ALIGNED;
/*
* ARRAY_MODE enum
*/
typedef enum ARRAY_MODE {
AM_LINEAR_GENERAL = 0x00000000,
AM_LINEAR_ALIGNED = 0x00000001,
AM_1D_TILED_THIN1 = 0x00000002,
AM_1D_TILED_THICK = 0x00000003,
AM_2D_TILED_THIN1 = 0x00000004,
AM_PRT_TILED_THIN1 = 0x00000005,
AM_PRT_2D_TILED_THIN1 = 0x00000006,
AM_2D_TILED_THICK = 0x00000007,
AM_2D_TILED_XTHICK = 0x00000008,
AM_PRT_TILED_THICK = 0x00000009,
AM_PRT_2D_TILED_THICK = 0x0000000a,
AM_PRT_3D_TILED_THIN1 = 0x0000000b,
AM_3D_TILED_THIN1 = 0x0000000c,
AM_3D_TILED_THICK = 0x0000000d,
AM_3D_TILED_XTHICK = 0x0000000e,
AM_PRT_3D_TILED_THICK = 0x0000000f,
} ARRAY_MODE;
/*
* PIPE_CONFIG enum
*/
typedef enum PIPE_CONFIG {
P2 = 0x00000000,
P4_8x16 = 0x00000004,
P4_16x16 = 0x00000005,
P4_16x32 = 0x00000006,
P4_32x32 = 0x00000007,
P8_16x16_8x16 = 0x00000008,
P8_16x32_8x16 = 0x00000009,
P8_32x32_8x16 = 0x0000000a,
P8_16x32_16x16 = 0x0000000b,
P8_32x32_16x16 = 0x0000000c,
P8_32x32_16x32 = 0x0000000d,
P8_32x64_32x32 = 0x0000000e,
P16_32x32_8x16 = 0x00000010,
P16_32x32_16x16 = 0x00000011,
P16_ADDR_SURF = 0x00000012,
} PIPE_CONFIG;
/*
* MICRO_TILE_MODE_NEW enum
*/
typedef enum MICRO_TILE_MODE_NEW {
DISPLAY_MICRO_TILING = 0x00000000,
THIN_MICRO_TILING = 0x00000001,
DEPTH_MICRO_TILING = 0x00000002,
ROTATED_MICRO_TILING = 0x00000003,
THICK_MICRO_TILING = 0x00000004,
} MICRO_TILE_MODE_NEW;
/*
* TILE_SPLIT enum
*/
typedef enum TILE_SPLIT {
SURF_TILE_SPLIT_64B = 0x00000000,
SURF_TILE_SPLIT_128B = 0x00000001,
SURF_TILE_SPLIT_256B = 0x00000002,
SURF_TILE_SPLIT_512B = 0x00000003,
SURF_TILE_SPLIT_1KB = 0x00000004,
SURF_TILE_SPLIT_2KB = 0x00000005,
SURF_TILE_SPLIT_4KB = 0x00000006,
} TILE_SPLIT;
/*
* BANK_WIDTH enum
*/
typedef enum BANK_WIDTH {
SURF_BANK_WIDTH_1 = 0x00000000,
SURF_BANK_WIDTH_2 = 0x00000001,
SURF_BANK_WIDTH_4 = 0x00000002,
SURF_BANK_WIDTH_8 = 0x00000003,
} BANK_WIDTH;
/*
* BANK_HEIGHT enum
*/
typedef enum BANK_HEIGHT {
SURF_BANK_HEIGHT_1 = 0x00000000,
SURF_BANK_HEIGHT_2 = 0x00000001,
SURF_BANK_HEIGHT_4 = 0x00000002,
SURF_BANK_HEIGHT_8 = 0x00000003,
} BANK_HEIGHT;
/*
* MACRO_TILE_ASPECT enum
*/
typedef enum MACRO_TILE_ASPECT {
SURF_MACRO_ASPECT_1 = 0x00000000,
SURF_MACRO_ASPECT_2 = 0x00000001,
SURF_MACRO_ASPECT_4 = 0x00000002,
SURF_MACRO_ASPECT_8 = 0x00000003,
} MACRO_TILE_ASPECT;
/*
* LEGACY_NUM_BANKS enum
*/
typedef enum LEGACY_NUM_BANKS {
SURF_2_BANK = 0x00000000,
SURF_4_BANK = 0x00000001,
SURF_8_BANK = 0x00000002,
SURF_16_BANK = 0x00000003,
} LEGACY_NUM_BANKS;
/*
* SWATH_HEIGHT enum
*/
typedef enum SWATH_HEIGHT {
SWATH_HEIGHT_1L = 0x00000000,
SWATH_HEIGHT_2L = 0x00000001,
SWATH_HEIGHT_4L = 0x00000002,
SWATH_HEIGHT_8L = 0x00000003,
SWATH_HEIGHT_16L = 0x00000004,
} SWATH_HEIGHT;
/*
* PTE_ROW_HEIGHT_LINEAR enum
*/
typedef enum PTE_ROW_HEIGHT_LINEAR {
PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
} PTE_ROW_HEIGHT_LINEAR;
/*
* CHUNK_SIZE enum
*/
typedef enum CHUNK_SIZE {
CHUNK_SIZE_1KB = 0x00000000,
CHUNK_SIZE_2KB = 0x00000001,
CHUNK_SIZE_4KB = 0x00000002,
CHUNK_SIZE_8KB = 0x00000003,
CHUNK_SIZE_16KB = 0x00000004,
CHUNK_SIZE_32KB = 0x00000005,
CHUNK_SIZE_64KB = 0x00000006,
} CHUNK_SIZE;
/*
* MIN_CHUNK_SIZE enum
*/
typedef enum MIN_CHUNK_SIZE {
NO_MIN_CHUNK_SIZE = 0x00000000,
MIN_CHUNK_SIZE_256B = 0x00000001,
MIN_CHUNK_SIZE_512B = 0x00000002,
MIN_CHUNK_SIZE_1024B = 0x00000003,
} MIN_CHUNK_SIZE;
/*
* META_CHUNK_SIZE enum
*/
typedef enum META_CHUNK_SIZE {
META_CHUNK_SIZE_1KB = 0x00000000,
META_CHUNK_SIZE_2KB = 0x00000001,
META_CHUNK_SIZE_4KB = 0x00000002,
META_CHUNK_SIZE_8KB = 0x00000003,
} META_CHUNK_SIZE;
/*
* MIN_META_CHUNK_SIZE enum
*/
typedef enum MIN_META_CHUNK_SIZE {
NO_MIN_META_CHUNK_SIZE = 0x00000000,
MIN_META_CHUNK_SIZE_64B = 0x00000001,
MIN_META_CHUNK_SIZE_128B = 0x00000002,
MIN_META_CHUNK_SIZE_256B = 0x00000003,
} MIN_META_CHUNK_SIZE;
/*
* DPTE_GROUP_SIZE enum
*/
typedef enum DPTE_GROUP_SIZE {
DPTE_GROUP_SIZE_64B = 0x00000000,
DPTE_GROUP_SIZE_128B = 0x00000001,
DPTE_GROUP_SIZE_256B = 0x00000002,
DPTE_GROUP_SIZE_512B = 0x00000003,
DPTE_GROUP_SIZE_1024B = 0x00000004,
DPTE_GROUP_SIZE_2048B = 0x00000005,
DPTE_GROUP_SIZE_4096B = 0x00000006,
DPTE_GROUP_SIZE_8192B = 0x00000007,
} DPTE_GROUP_SIZE;
/*
* MPTE_GROUP_SIZE enum
*/
typedef enum MPTE_GROUP_SIZE {
MPTE_GROUP_SIZE_64B = 0x00000000,
MPTE_GROUP_SIZE_128B = 0x00000001,
MPTE_GROUP_SIZE_256B = 0x00000002,
MPTE_GROUP_SIZE_512B = 0x00000003,
MPTE_GROUP_SIZE_1024B = 0x00000004,
MPTE_GROUP_SIZE_2048B = 0x00000005,
MPTE_GROUP_SIZE_4096B = 0x00000006,
MPTE_GROUP_SIZE_8192B = 0x00000007,
} MPTE_GROUP_SIZE;
/*
* HUBP_BLANK_EN enum
*/
typedef enum HUBP_BLANK_EN {
HUBP_BLANK_SW_DEASSERT = 0x00000000,
HUBP_BLANK_SW_ASSERT = 0x00000001,
} HUBP_BLANK_EN;
/*
* HUBP_DISABLE enum
*/
typedef enum HUBP_DISABLE {
HUBP_ENABLED = 0x00000000,
HUBP_DISABLED = 0x00000001,
} HUBP_DISABLE;
/*
* HUBP_TTU_DISABLE enum
*/
typedef enum HUBP_TTU_DISABLE {
HUBP_TTU_ENABLED = 0x00000000,
HUBP_TTU_DISABLED = 0x00000001,
} HUBP_TTU_DISABLE;
/*
* HUBP_NO_OUTSTANDING_REQ enum
*/
typedef enum HUBP_NO_OUTSTANDING_REQ {
OUTSTANDING_REQ = 0x00000000,
NO_OUTSTANDING_REQ = 0x00000001,
} HUBP_NO_OUTSTANDING_REQ;
/*
* HUBP_IN_BLANK enum
*/
typedef enum HUBP_IN_BLANK {
HUBP_IN_ACTIVE = 0x00000000,
HUBP_IN_VBLANK = 0x00000001,
} HUBP_IN_BLANK;
/*
* HUBP_VTG_SEL enum
*/
typedef enum HUBP_VTG_SEL {
VTG_SEL_0 = 0x00000000,
VTG_SEL_1 = 0x00000001,
VTG_SEL_2 = 0x00000002,
VTG_SEL_3 = 0x00000003,
VTG_SEL_4 = 0x00000004,
VTG_SEL_5 = 0x00000005,
} HUBP_VTG_SEL;
/*
* HUBP_VREADY_AT_OR_AFTER_VSYNC enum
*/
typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
VREADY_BEFORE_VSYNC = 0x00000000,
VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
} HUBP_VREADY_AT_OR_AFTER_VSYNC;
/*
* VMPG_SIZE enum
*/
typedef enum VMPG_SIZE {
VMPG_SIZE_4KB = 0x00000000,
VMPG_SIZE_64KB = 0x00000001,
} VMPG_SIZE;
/*
* HUBP_MEASURE_WIN_MODE_DCFCLK enum
*/
typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
} HUBP_MEASURE_WIN_MODE_DCFCLK;
/*******************************************************
* HUBPREQ Enums
*******************************************************/
/*
* SURFACE_TMZ enum
*/
typedef enum SURFACE_TMZ {
SURFACE_IS_NOT_TMZ = 0x00000000,
SURFACE_IS_TMZ = 0x00000001,
} SURFACE_TMZ;
/*
* SURFACE_DCC enum
*/
typedef enum SURFACE_DCC {
SURFACE_IS_NOT_DCC = 0x00000000,
SURFACE_IS_DCC = 0x00000001,
} SURFACE_DCC;
/*
* SURFACE_DCC_IND_64B enum
*/
typedef enum SURFACE_DCC_IND_64B {
SURFACE_DCC_IS_NOT_IND_64B = 0x00000000,
SURFACE_DCC_IS_IND_64B = 0x00000001,
} SURFACE_DCC_IND_64B;
/*
* SURFACE_FLIP_TYPE enum
*/
typedef enum SURFACE_FLIP_TYPE {
SURFACE_V_FLIP = 0x00000000,
SURFACE_I_FLIP = 0x00000001,
} SURFACE_FLIP_TYPE;
/*
* SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
*/
typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
FLIP_ANY_FRAME = 0x00000000,
FLIP_LEFT_EYE = 0x00000001,
FLIP_RIGHT_EYE = 0x00000002,
SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
} SURFACE_FLIP_MODE_FOR_STEREOSYNC;
/*
* SURFACE_UPDATE_LOCK enum
*/
typedef enum SURFACE_UPDATE_LOCK {
SURFACE_UPDATE_IS_UNLOCKED = 0x00000000,
SURFACE_UPDATE_IS_LOCKED = 0x00000001,
} SURFACE_UPDATE_LOCK;
/*
* SURFACE_FLIP_IN_STEREOSYNC enum
*/
typedef enum SURFACE_FLIP_IN_STEREOSYNC {
SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000,
SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001,
} SURFACE_FLIP_IN_STEREOSYNC;
/*
* SURFACE_FLIP_STEREO_SELECT_DISABLE enum
*/
typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000,
SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001,
} SURFACE_FLIP_STEREO_SELECT_DISABLE;
/*
* SURFACE_FLIP_STEREO_SELECT_POLARITY enum
*/
typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
} SURFACE_FLIP_STEREO_SELECT_POLARITY;
/*
* SURFACE_INUSE_RAED_NO_LATCH enum
*/
typedef enum SURFACE_INUSE_RAED_NO_LATCH {
SURFACE_INUSE_IS_LATCHED = 0x00000000,
SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001,
} SURFACE_INUSE_RAED_NO_LATCH;
/*
* INT_MASK enum
*/
typedef enum INT_MASK {
INT_DISABLED = 0x00000000,
INT_ENABLED = 0x00000001,
} INT_MASK;
/*
* SURFACE_FLIP_INT_TYPE enum
*/
typedef enum SURFACE_FLIP_INT_TYPE {
SURFACE_FLIP_INT_LEVEL = 0x00000000,
SURFACE_FLIP_INT_PULSE = 0x00000001,
} SURFACE_FLIP_INT_TYPE;
/*
* SURFACE_FLIP_AWAY_INT_TYPE enum
*/
typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000,
SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001,
} SURFACE_FLIP_AWAY_INT_TYPE;
/*
* SURFACE_FLIP_VUPDATE_SKIP_NUM enum
*/
typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000,
SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001,
SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002,
SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003,
SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004,
SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005,
SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006,
SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007,
SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008,
SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009,
SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a,
SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b,
SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c,
SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d,
SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e,
SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f,
} SURFACE_FLIP_VUPDATE_SKIP_NUM;
/*
* DFQ_SIZE enum
*/
typedef enum DFQ_SIZE {
DFQ_SIZE_0 = 0x00000000,
DFQ_SIZE_1 = 0x00000001,
DFQ_SIZE_2 = 0x00000002,
DFQ_SIZE_3 = 0x00000003,
DFQ_SIZE_4 = 0x00000004,
DFQ_SIZE_5 = 0x00000005,
DFQ_SIZE_6 = 0x00000006,
DFQ_SIZE_7 = 0x00000007,
} DFQ_SIZE;
/*
* DFQ_MIN_FREE_ENTRIES enum
*/
typedef enum DFQ_MIN_FREE_ENTRIES {
DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
} DFQ_MIN_FREE_ENTRIES;
/*
* DFQ_NUM_ENTRIES enum
*/
typedef enum DFQ_NUM_ENTRIES {
DFQ_NUM_ENTRIES_0 = 0x00000000,
DFQ_NUM_ENTRIES_1 = 0x00000001,
DFQ_NUM_ENTRIES_2 = 0x00000002,
DFQ_NUM_ENTRIES_3 = 0x00000003,
DFQ_NUM_ENTRIES_4 = 0x00000004,
DFQ_NUM_ENTRIES_5 = 0x00000005,
DFQ_NUM_ENTRIES_6 = 0x00000006,
DFQ_NUM_ENTRIES_7 = 0x00000007,
DFQ_NUM_ENTRIES_8 = 0x00000008,
} DFQ_NUM_ENTRIES;
/*
* FLIP_RATE enum
*/
typedef enum FLIP_RATE {
FLIP_RATE_0 = 0x00000000,
FLIP_RATE_1 = 0x00000001,
FLIP_RATE_2 = 0x00000002,
FLIP_RATE_3 = 0x00000003,
FLIP_RATE_4 = 0x00000004,
FLIP_RATE_5 = 0x00000005,
FLIP_RATE_6 = 0x00000006,
FLIP_RATE_7 = 0x00000007,
} FLIP_RATE;
/*******************************************************
* HUBPRET Enums
*******************************************************/
/*
* DETILE_BUFFER_PACKER_ENABLE enum
*/
typedef enum DETILE_BUFFER_PACKER_ENABLE {
DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000,
DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001,
} DETILE_BUFFER_PACKER_ENABLE;
/*
* CROSSBAR_FOR_ALPHA enum
*/
typedef enum CROSSBAR_FOR_ALPHA {
ALPHA_DATA_ON_ALPHA_PORT = 0x00000000,
ALPHA_DATA_ON_Y_G_PORT = 0x00000001,
ALPHA_DATA_ON_CB_B_PORT = 0x00000002,
ALPHA_DATA_ON_CR_R_PORT = 0x00000003,
} CROSSBAR_FOR_ALPHA;
/*
* CROSSBAR_FOR_Y_G enum
*/
typedef enum CROSSBAR_FOR_Y_G {
Y_G_DATA_ON_ALPHA_PORT = 0x00000000,
Y_G_DATA_ON_Y_G_PORT = 0x00000001,
Y_G_DATA_ON_CB_B_PORT = 0x00000002,
Y_G_DATA_ON_CR_R_PORT = 0x00000003,
} CROSSBAR_FOR_Y_G;
/*
* CROSSBAR_FOR_CB_B enum
*/
typedef enum CROSSBAR_FOR_CB_B {
CB_B_DATA_ON_ALPHA_PORT = 0x00000000,
CB_B_DATA_ON_Y_G_PORT = 0x00000001,
CB_B_DATA_ON_CB_B_PORT = 0x00000002,
CB_B_DATA_ON_CR_R_PORT = 0x00000003,
} CROSSBAR_FOR_CB_B;
/*
* CROSSBAR_FOR_CR_R enum
*/
typedef enum CROSSBAR_FOR_CR_R {
CR_R_DATA_ON_ALPHA_PORT = 0x00000000,
CR_R_DATA_ON_Y_G_PORT = 0x00000001,
CR_R_DATA_ON_CB_B_PORT = 0x00000002,
CR_R_DATA_ON_CR_R_PORT = 0x00000003,
} CROSSBAR_FOR_CR_R;
/*
* DET_MEM_PWR_LIGHT_SLEEP_MODE enum
*/
typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE {
DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
} DET_MEM_PWR_LIGHT_SLEEP_MODE;
/*
* PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
*/
typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
/*******************************************************
* CURSOR Enums
*******************************************************/
/*
* CURSOR_ENABLE enum
*/
typedef enum CURSOR_ENABLE {
CURSOR_IS_DISABLE = 0x00000000,
CURSOR_IS_ENABLE = 0x00000001,
} CURSOR_ENABLE;
/*
* CURSOR_2X_MAGNIFY enum
*/
typedef enum CURSOR_2X_MAGNIFY {
CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000,
CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001,
} CURSOR_2X_MAGNIFY;
/*
* CURSOR_MODE enum
*/
typedef enum CURSOR_MODE {
CURSOR_MONO_2BIT = 0x00000000,
CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001,
CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004,
CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005,
} CURSOR_MODE;
/*
* CURSOR_SURFACE_TMZ enum
*/
typedef enum CURSOR_SURFACE_TMZ {
CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000,
CURSOR_SURFACE_IS_TMZ = 0x00000001,
} CURSOR_SURFACE_TMZ;
/*
* CURSOR_SNOOP enum
*/
typedef enum CURSOR_SNOOP {
CURSOR_IS_NOT_SNOOP = 0x00000000,
CURSOR_IS_SNOOP = 0x00000001,
} CURSOR_SNOOP;
/*
* CURSOR_SYSTEM enum
*/
typedef enum CURSOR_SYSTEM {
CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000,
CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001,
} CURSOR_SYSTEM;
/*
* CURSOR_PITCH enum
*/
typedef enum CURSOR_PITCH {
CURSOR_PITCH_64_PIXELS = 0x00000000,
CURSOR_PITCH_128_PIXELS = 0x00000001,
CURSOR_PITCH_256_PIXELS = 0x00000002,
} CURSOR_PITCH;
/*
* CURSOR_LINES_PER_CHUNK enum
*/
typedef enum CURSOR_LINES_PER_CHUNK {
CURSOR_LINE_PER_CHUNK_1 = 0x00000000,
CURSOR_LINE_PER_CHUNK_2 = 0x00000001,
CURSOR_LINE_PER_CHUNK_4 = 0x00000002,
CURSOR_LINE_PER_CHUNK_8 = 0x00000003,
CURSOR_LINE_PER_CHUNK_16 = 0x00000004,
} CURSOR_LINES_PER_CHUNK;
/*
* CURSOR_PERFMON_LATENCY_MEASURE_EN enum
*/
typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
} CURSOR_PERFMON_LATENCY_MEASURE_EN;
/*
* CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
*/
typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
} CURSOR_PERFMON_LATENCY_MEASURE_SEL;
/*
* CURSOR_STEREO_EN enum
*/
typedef enum CURSOR_STEREO_EN {
CURSOR_STEREO_IS_DISABLED = 0x00000000,
CURSOR_STEREO_IS_ENABLED = 0x00000001,
} CURSOR_STEREO_EN;
/*
* CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
*/
typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
/*
* CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
*/
typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
} CROB_MEM_PWR_LIGHT_SLEEP_MODE;
/*
* DMDATA_UPDATED enum
*/
typedef enum DMDATA_UPDATED {
DMDATA_NOT_UPDATED = 0x00000000,
DMDATA_WAS_UPDATED = 0x00000001,
} DMDATA_UPDATED;
/*
* DMDATA_REPEAT enum
*/
typedef enum DMDATA_REPEAT {
DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000,
DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
} DMDATA_REPEAT;
/*
* DMDATA_MODE enum
*/
typedef enum DMDATA_MODE {
DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000,
DMDATA_HARDWARE_UPDATE_MODE = 0x00000001,
} DMDATA_MODE;
/*
* DMDATA_QOS_MODE enum
*/
typedef enum DMDATA_QOS_MODE {
DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000,
DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001,
} DMDATA_QOS_MODE;
/*
* DMDATA_DONE enum
*/
typedef enum DMDATA_DONE {
DMDATA_NOT_SENT_TO_DIG = 0x00000000,
DMDATA_SENT_TO_DIG = 0x00000001,
} DMDATA_DONE;
/*
* DMDATA_UNDERFLOW enum
*/
typedef enum DMDATA_UNDERFLOW {
DMDATA_NOT_UNDERFLOW = 0x00000000,
DMDATA_UNDERFLOWED = 0x00000001,
} DMDATA_UNDERFLOW;
/*
* DMDATA_UNDERFLOW_CLEAR enum
*/
typedef enum DMDATA_UNDERFLOW_CLEAR {
DMDATA_DONT_CLEAR = 0x00000000,
DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001,
} DMDATA_UNDERFLOW_CLEAR;
/*******************************************************
* HUBPXFC Enums
*******************************************************/
/*
* HUBP_XFC_PIXEL_FORMAT_ENUM enum
*/
typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM {
HUBP_XFC_PIXEL_IS_32BPP = 0x00000000,
HUBP_XFC_PIXEL_IS_64BPP = 0x00000001,
} HUBP_XFC_PIXEL_FORMAT_ENUM;
/*
* HUBP_XFC_FRAME_MODE_ENUM enum
*/
typedef enum HUBP_XFC_FRAME_MODE_ENUM {
HUBP_XFC_PARTIAL_FRAME_MODE = 0x00000000,
HUBP_XFC_FULL_FRAME_MODE = 0x00000001,
} HUBP_XFC_FRAME_MODE_ENUM;
/*
* HUBP_XFC_CHUNK_SIZE_ENUM enum
*/
typedef enum HUBP_XFC_CHUNK_SIZE_ENUM {
HUBP_XFC_CHUNK_SIZE_256B = 0x00000000,
HUBP_XFC_CHUNK_SIZE_512B = 0x00000001,
HUBP_XFC_CHUNK_SIZE_1KB = 0x00000002,
HUBP_XFC_CHUNK_SIZE_2KB = 0x00000003,
HUBP_XFC_CHUNK_SIZE_4KB = 0x00000004,
HUBP_XFC_CHUNK_SIZE_8KB = 0x00000005,
HUBP_XFC_CHUNK_SIZE_16KB = 0x00000006,
HUBP_XFC_CHUNK_SIZE_32KB = 0x00000007,
} HUBP_XFC_CHUNK_SIZE_ENUM;
/*******************************************************
* XFC Enums
*******************************************************/
/*
* MMHUBBUB_XFC_XFCMON_MODE_ENUM enum
*/
typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM {
MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0x00000000,
MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 0x00000001,
MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 0x00000002,
} MMHUBBUB_XFC_XFCMON_MODE_ENUM;
/*
* MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum
*/
typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM {
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0x00000000,
MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 0x00000001,
} MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM;
/*******************************************************
* XFCP Enums
*******************************************************/
/*
* MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum
*/
typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM {
MMHUBBUB_XFC_PIXEL_IS_32BPP = 0x00000000,
MMHUBBUB_XFC_PIXEL_IS_64BPP = 0x00000001,
} MMHUBBUB_XFC_PIXEL_FORMAT_ENUM;
/*
* MMHUBBUB_XFC_FRAME_MODE_ENUM enum
*/
typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM {
MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0x00000000,
MMHUBBUB_XFC_FULL_FRAME_MODE = 0x00000001,
} MMHUBBUB_XFC_FRAME_MODE_ENUM;
/*******************************************************
* MPC_CFG Enums
*******************************************************/
/*
* MPC_CFG_MPC_TEST_CLK_SEL enum
*/
typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000,
MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001,
MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002,
MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003,
} MPC_CFG_MPC_TEST_CLK_SEL;
/*
* MPC_CRC_CALC_MODE enum
*/
typedef enum MPC_CRC_CALC_MODE {
MPC_CRC_ONE_SHOT_MODE = 0x00000000,
MPC_CRC_CONTINUOUS_MODE = 0x00000001,
} MPC_CRC_CALC_MODE;
/*
* MPC_CRC_CALC_STEREO_MODE enum
*/
typedef enum MPC_CRC_CALC_STEREO_MODE {
MPC_CRC_STEREO_MODE_LEFT = 0x00000000,
MPC_CRC_STEREO_MODE_RIGHT = 0x00000001,
MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002,
MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003,
} MPC_CRC_CALC_STEREO_MODE;
/*
* MPC_CRC_CALC_INTERLACE_MODE enum
*/
typedef enum MPC_CRC_CALC_INTERLACE_MODE {
MPC_CRC_INTERLACE_MODE_TOP = 0x00000000,
MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003,
} MPC_CRC_CALC_INTERLACE_MODE;
/*
* MPC_CRC_SOURCE_SELECT enum
*/
typedef enum MPC_CRC_SOURCE_SELECT {
MPC_CRC_SOURCE_SEL_DPP = 0x00000000,
MPC_CRC_SOURCE_SEL_OPP = 0x00000001,
MPC_CRC_SOURCE_SEL_DWB = 0x00000002,
MPC_CRC_SOURCE_SEL_OTHER = 0x00000003,
} MPC_CRC_SOURCE_SELECT;
/*
* MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
*/
typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
/*
* MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
*/
typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
/*
* MPC_CFG_CFG_VUPDATE_LOCK_SET enum
*/
typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
} MPC_CFG_CFG_VUPDATE_LOCK_SET;
/*
* MPC_CFG_ADR_VUPDATE_LOCK_SET enum
*/
typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
} MPC_CFG_ADR_VUPDATE_LOCK_SET;
/*
* MPC_CFG_CUR_VUPDATE_LOCK_SET enum
*/
typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
} MPC_CFG_CUR_VUPDATE_LOCK_SET;
/*
* MPC_OUT_RATE_CONTROL_DISABLE_SET enum
*/
typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000,
MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001,
} MPC_OUT_RATE_CONTROL_DISABLE_SET;
/*
* MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
*/
typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
/*******************************************************
* MPC_OCSC Enums
*******************************************************/
/*
* MPC_OCSC_COEF_FORMAT enum
*/
typedef enum MPC_OCSC_COEF_FORMAT {
MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000,
MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001,
} MPC_OCSC_COEF_FORMAT;
/*
* MPC_OUT_CSC_MODE enum
*/
typedef enum MPC_OUT_CSC_MODE {
MPC_OUT_CSC_MODE_0 = 0x00000000,
MPC_OUT_CSC_MODE_1 = 0x00000001,
MPC_OUT_CSC_MODE_2 = 0x00000002,
MPC_OUT_CSC_MODE_RSV = 0x00000003,
} MPC_OUT_CSC_MODE;
/*******************************************************
* MPCC Enums
*******************************************************/
/*
* MPCC_CONTROL_MPCC_MODE enum
*/
typedef enum MPCC_CONTROL_MPCC_MODE {
MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000,
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002,
MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003,
} MPCC_CONTROL_MPCC_MODE;
/*
* MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
*/
typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
/*
* MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
*/
typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
/*
* MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
*/
typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
/*
* MPCC_SM_CONTROL_MPCC_SM_EN enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_EN;
/*
* MPCC_SM_CONTROL_MPCC_SM_MODE enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
} MPCC_SM_CONTROL_MPCC_SM_MODE;
/*
* MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
/*
* MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001,
} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
/*
* MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
/*
* MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
*/
typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
/*
* MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum
*/
typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK {
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000,
MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001,
} MPCC_STALL_STATUS_MPCC_STALL_INT_ACK;
/*
* MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum
*/
typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK {
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0x00000000,
MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 0x00000001,
} MPCC_STALL_STATUS_MPCC_STALL_INT_MASK;
/*
* MPCC_BG_COLOR_BPC enum
*/
typedef enum MPCC_BG_COLOR_BPC {
MPCC_BG_COLOR_BPC_8bit = 0x00000000,
MPCC_BG_COLOR_BPC_9bit = 0x00000001,
MPCC_BG_COLOR_BPC_10bit = 0x00000002,
MPCC_BG_COLOR_BPC_11bit = 0x00000003,
MPCC_BG_COLOR_BPC_12bit = 0x00000004,
} MPCC_BG_COLOR_BPC;
/*
* MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
*/
typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000,
MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001,
} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
/*******************************************************
* MPCC_OGAM Enums
*******************************************************/
/*
* MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
*/
typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
/*
* MPCC_OGAM_MODE_MPCC_OGAM_MODE enum
*/
typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE {
MPCC_OGAM_MODE_0 = 0x00000000,
MPCC_OGAM_MODE_1 = 0x00000001,
MPCC_OGAM_MODE_2 = 0x00000002,
MPCC_OGAM_MODE_RSV = 0x00000003,
} MPCC_OGAM_MODE_MPCC_OGAM_MODE;
/*******************************************************
* DPG Enums
*******************************************************/
/*
* ENUM_DPG_EN enum
*/
typedef enum ENUM_DPG_EN {
ENUM_DPG_DISABLE = 0x00000000,
ENUM_DPG_ENABLE = 0x00000001,
} ENUM_DPG_EN;
/*
* ENUM_DPG_MODE enum
*/
typedef enum ENUM_DPG_MODE {
ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000,
ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001,
ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002,
ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003,
ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004,
ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005,
ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006,
ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007,
} ENUM_DPG_MODE;
/*
* ENUM_DPG_DYNAMIC_RANGE enum
*/
typedef enum ENUM_DPG_DYNAMIC_RANGE {
ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000,
ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001,
} ENUM_DPG_DYNAMIC_RANGE;
/*
* ENUM_DPG_BIT_DEPTH enum
*/
typedef enum ENUM_DPG_BIT_DEPTH {
ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000,
ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001,
ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002,
ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003,
} ENUM_DPG_BIT_DEPTH;
/*
* ENUM_DPG_FIELD_POLARITY enum
*/
typedef enum ENUM_DPG_FIELD_POLARITY {
ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
} ENUM_DPG_FIELD_POLARITY;
/*******************************************************
* FMT Enums
*******************************************************/
/*
* FMT_CONTROL_PIXEL_ENCODING enum
*/
typedef enum FMT_CONTROL_PIXEL_ENCODING {
FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
} FMT_CONTROL_PIXEL_ENCODING;
/*
* FMT_CONTROL_SUBSAMPLING_MODE enum
*/
typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
} FMT_CONTROL_SUBSAMPLING_MODE;
/*
* FMT_CONTROL_SUBSAMPLING_ORDER enum
*/
typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
} FMT_CONTROL_SUBSAMPLING_ORDER;
/*
* FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
*/
typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
/*
* FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
/*
* FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
/*
* FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
/*
* FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
/*
* FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
/*
* FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
/*
* FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
/*
* FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
*/
typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
/*
* FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
*/
typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
/*
* FMT_CLAMP_CNTL_COLOR_FORMAT enum
*/
typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
} FMT_CLAMP_CNTL_COLOR_FORMAT;
/*
* FMT_SPATIAL_DITHER_MODE enum
*/
typedef enum FMT_SPATIAL_DITHER_MODE {
FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
} FMT_SPATIAL_DITHER_MODE;
/*
* FMT_DYNAMIC_EXP_MODE enum
*/
typedef enum FMT_DYNAMIC_EXP_MODE {
FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
} FMT_DYNAMIC_EXP_MODE;
/*
* FMTMEM_PWR_FORCE_CTRL enum
*/
typedef enum FMTMEM_PWR_FORCE_CTRL {
FMTMEM_NO_FORCE_REQUEST = 0x00000000,
FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
} FMTMEM_PWR_FORCE_CTRL;
/*
* FMTMEM_PWR_DIS_CTRL enum
*/
typedef enum FMTMEM_PWR_DIS_CTRL {
FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
} FMTMEM_PWR_DIS_CTRL;
/*
* FMT_POWER_STATE_ENUM enum
*/
typedef enum FMT_POWER_STATE_ENUM {
FMT_POWER_STATE_ENUM_ON = 0x00000000,
FMT_POWER_STATE_ENUM_LS = 0x00000001,
FMT_POWER_STATE_ENUM_DS = 0x00000002,
FMT_POWER_STATE_ENUM_SD = 0x00000003,
} FMT_POWER_STATE_ENUM;
/*
* FMT_STEREOSYNC_OVERRIDE_CONTROL enum
*/
typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000,
FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001,
} FMT_STEREOSYNC_OVERRIDE_CONTROL;
/*
* FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
*/
typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
/*
* FMT_FRAME_RANDOM_ENABLE_CONTROL enum
*/
typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001,
} FMT_FRAME_RANDOM_ENABLE_CONTROL;
/*
* FMT_RGB_RANDOM_ENABLE_CONTROL enum
*/
typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000,
FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001,
} FMT_RGB_RANDOM_ENABLE_CONTROL;
/*
* ENUM_FMT_PTI_FIELD_POLARITY enum
*/
typedef enum ENUM_FMT_PTI_FIELD_POLARITY {
ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
} ENUM_FMT_PTI_FIELD_POLARITY;
/*******************************************************
* OPP_PIPE Enums
*******************************************************/
/*
* OPP_PIPE_CLOCK_ENABLE_CONTROL enum
*/
typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
OPP_PIPE_CLOCK_DISABLE = 0x00000000,
OPP_PIPE_CLOCK_ENABLE = 0x00000001,
} OPP_PIPE_CLOCK_ENABLE_CONTROL;
/*
* OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
*/
typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000,
OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001,
} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
/*******************************************************
* OPP_PIPE_CRC Enums
*******************************************************/
/*
* OPP_PIPE_CRC_EN enum
*/
typedef enum OPP_PIPE_CRC_EN {
OPP_PIPE_CRC_DISABLE = 0x00000000,
OPP_PIPE_CRC_ENABLE = 0x00000001,
} OPP_PIPE_CRC_EN;
/*
* OPP_PIPE_CRC_CONT_EN enum
*/
typedef enum OPP_PIPE_CRC_CONT_EN {
OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000,
OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001,
} OPP_PIPE_CRC_CONT_EN;
/*
* OPP_PIPE_CRC_STEREO_MODE enum
*/
typedef enum OPP_PIPE_CRC_STEREO_MODE {
OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000,
OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001,
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
} OPP_PIPE_CRC_STEREO_MODE;
/*
* OPP_PIPE_CRC_STEREO_EN enum
*/
typedef enum OPP_PIPE_CRC_STEREO_EN {
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
} OPP_PIPE_CRC_STEREO_EN;
/*
* OPP_PIPE_CRC_INTERLACE_MODE enum
*/
typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000,
OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
} OPP_PIPE_CRC_INTERLACE_MODE;
/*
* OPP_PIPE_CRC_INTERLACE_EN enum
*/
typedef enum OPP_PIPE_CRC_INTERLACE_EN {
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
} OPP_PIPE_CRC_INTERLACE_EN;
/*
* OPP_PIPE_CRC_PIXEL_SELECT enum
*/
typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000,
OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001,
OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002,
OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003,
} OPP_PIPE_CRC_PIXEL_SELECT;
/*
* OPP_PIPE_CRC_SOURCE_SELECT enum
*/
typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000,
OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001,
} OPP_PIPE_CRC_SOURCE_SELECT;
/*
* OPP_PIPE_CRC_ONE_SHOT_PENDING enum
*/
typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001,
} OPP_PIPE_CRC_ONE_SHOT_PENDING;
/*******************************************************
* OPP_TOP Enums
*******************************************************/
/*
* OPP_TOP_CLOCK_GATING_CONTROL enum
*/
typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000,
OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001,
} OPP_TOP_CLOCK_GATING_CONTROL;
/*
* OPP_TOP_CLOCK_ENABLE_STATUS enum
*/
typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000,
OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001,
} OPP_TOP_CLOCK_ENABLE_STATUS;
/*
* OPP_TEST_CLK_SEL_CONTROL enum
*/
typedef enum OPP_TEST_CLK_SEL_CONTROL {
OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001,
OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002,
OPP_TEST_CLK_SEL_RESERVED0 = 0x00000003,
OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000004,
OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000005,
OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x00000006,
OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x00000007,
OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 0x00000008,
OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 0x00000009,
} OPP_TEST_CLK_SEL_CONTROL;
/*******************************************************
* OTG Enums
*******************************************************/
/*
* OTG_CONTROL_OTG_START_POINT_CNTL enum
*/
typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000,
OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001,
} OTG_CONTROL_OTG_START_POINT_CNTL;
/*
* OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
*/
typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001,
} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
/*
* OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
*/
typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
/*
* OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
*/
typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
/*
* OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum
*/
typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE {
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
} OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE;
/*
* OTG_CONTROL_OTG_SOF_PULL_EN enum
*/
typedef enum OTG_CONTROL_OTG_SOF_PULL_EN {
OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0x00000000,
OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 0x00000001,
} OTG_CONTROL_OTG_SOF_PULL_EN;
/*
* OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
/*
* OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
/*
* OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN {
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN;
/*
* OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
/*
* OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
/*
* OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
*/
typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
/*
* OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
*/
typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
/*
* OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
*/
typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
/*
* OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
*/
typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
/*
* OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
*/
typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
/*
* OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
*/
typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
/*
* OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
*/
typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
/*
* OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
*/
typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 0x00000005,
} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
/*
* OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
*/
typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
/*
* OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
*/
typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 0x00000004,
OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 0x00000005,
} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
/*
* OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
*/
typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
/*
* OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
*/
typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000,
OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001,
} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
/*
* OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
*/
typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
/*
* OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
*/
typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000,
OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001,
} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
/*
* OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
*/
typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
/*
* OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
*/
typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
/*
* OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
*/
typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
/*
* OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
*/
typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
/*