| # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| %YAML 1.2 |
| --- |
| $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| title: Marvell Armada 3720 UART clocks |
| |
| maintainers: |
| - Pali Rohár <pali@kernel.org> |
| |
| properties: |
| compatible: |
| const: marvell,armada-3700-uart-clock |
| |
| reg: |
| items: |
| - description: UART Clock Control Register |
| - description: UART 2 Baud Rate Divisor Register |
| |
| clocks: |
| description: | |
| List of parent clocks suitable for UART from following set: |
| "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal" |
| UART clock can use one from this set and when more are provided |
| then kernel would choose and configure the most suitable one. |
| It is suggest to specify at least one TBG clock to achieve |
| baudrates above 230400 and also to specify clock which bootloader |
| used for UART (most probably xtal) for smooth boot log on UART. |
| |
| clock-names: |
| items: |
| - const: TBG-A-P |
| - const: TBG-B-P |
| - const: TBG-A-S |
| - const: TBG-B-S |
| - const: xtal |
| minItems: 1 |
| |
| '#clock-cells': |
| const: 1 |
| |
| required: |
| - compatible |
| - reg |
| - clocks |
| - clock-names |
| - '#clock-cells' |
| |
| additionalProperties: false |
| |
| examples: |
| - | |
| uartclk: clock-controller@12010 { |
| compatible = "marvell,armada-3700-uart-clock"; |
| reg = <0x12010 0x4>, <0x12210 0x4>; |
| clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>; |
| clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal"; |
| #clock-cells = <1>; |
| }; |