| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2019 NXP |
| * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de> |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8mp-debix-som-a.dtsi" |
| |
| / { |
| model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08"; |
| compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a", |
| "fsl,imx8mp"; |
| |
| aliases { |
| ethernet0 = &eqos; |
| ethernet1 = &fec; |
| }; |
| |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "BB_VDD3V3"; |
| /* Required timings for ethernet phy's */ |
| startup-delay-us = <50000>; |
| off-on-delay-us = <110000>; |
| gpio = <&expander0 10 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-name = "BB_VDD5V"; |
| gpio = <&expander0 9 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| regulator-som-vdd1v8 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-name = "SOM_VDD1V8_SW"; |
| gpio = <&expander0 12 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-always-on; |
| }; |
| |
| regulator-som-vdd3v3 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "SOM_VDD3V3_SW"; |
| gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-always-on; |
| }; |
| |
| reg_csi1_1v8: regulator-csi1-vdd1v8 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-name = "CSI1_VDD1V8"; |
| gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <®_baseboard_vdd3v3>; |
| }; |
| |
| reg_csi1_3v3: regulator-csi1-vdd3v3 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "CSI1_VDD3V3"; |
| gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <®_vdd5v0>; |
| }; |
| |
| reg_csi2_1v8: regulator-csi2-vdd1v8 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_csi2_1v8>; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-name = "CSI2_VDD1V8"; |
| gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <®_baseboard_vdd3v3>; |
| }; |
| |
| reg_csi2_3v3: regulator-csi2-vdd3v3 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_csi2_3v3>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "CSI2_VDD3V3"; |
| gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <®_vdd5v0>; |
| }; |
| |
| regulator-vbus-usb20 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-name = "USB20_5V"; |
| gpio = <&expander1 14 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-always-on; |
| vin-supply = <®_baseboard_vdd5v0>; |
| }; |
| |
| regulator-vbus-usb30 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-name = "USB30_5V"; |
| gpio = <&expander1 12 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| regulator-always-on; |
| vin-supply = <®_baseboard_vdd5v0>; |
| }; |
| |
| reg_vdd5v0: regulator-vdd5v0 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-name = "VDD_5V"; |
| gpio = <&expander0 8 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &eqos { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_eqos>; |
| nvmem-cells = <ðmac1>; |
| nvmem-cell-names = "mac-address"; |
| phy-supply = <®_baseboard_vdd3v3>; |
| phy-handle = <ðphy0>; |
| phy-mode = "rgmii-id"; |
| status = "okay"; |
| |
| mdio { |
| compatible = "snps,dwmac-mdio"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <20000>; |
| reset-deassert-us = <150000>; |
| eee-broken-1000t; |
| realtek,clkout-disable; |
| }; |
| }; |
| }; |
| |
| &fec { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec>; |
| nvmem-cells = <ðmac2>; |
| nvmem-cell-names = "mac-address"; |
| phy-supply = <®_baseboard_vdd3v3>; |
| phy-handle = <ðphy1>; |
| phy-mode = "rgmii-id"; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <20000>; |
| reset-deassert-us = <150000>; |
| eee-broken-1000t; |
| realtek,clkout-disable; |
| }; |
| }; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_vdd5v0>; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_vdd5v0>; |
| status = "okay"; |
| }; |
| |
| &flexspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexspi0>; |
| status = "okay"; |
| |
| flash: flash@0 { |
| compatible = "jedec,spi-nor"; |
| reg = <0>; |
| spi-max-frequency = <80000000>; |
| spi-tx-bus-width = <1>; |
| spi-rx-bus-width = <4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| }; |
| |
| &i2c4 { |
| expander0: gpio@20 { |
| compatible = "nxp,pca9535"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <0x02>; |
| }; |
| |
| expander1: gpio@23 { |
| compatible = "nxp,pca9535"; |
| reg = <0x23>; |
| gpio-controller; |
| #gpio-cells = <0x02>; |
| |
| /* |
| * Since USB1 is bound to peripheral mode we need to ensure |
| * that VBUS is turned off. |
| */ |
| usb30-otg-hog { |
| gpio-hog; |
| gpios = <13 GPIO_ACTIVE_HIGH>; |
| output-low; |
| line-name = "USB30_OTG_EN"; |
| }; |
| }; |
| |
| rtc@51 { |
| compatible = "haoyu,hym8563"; |
| reg = <0x51>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_rtc>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <3 IRQ_TYPE_EDGE_FALLING>; |
| #clock-cells = <0>; |
| }; |
| |
| eeprom@52 { |
| compatible = "atmel,24c02"; |
| reg = <0x52>; |
| pagesize = <16>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| /* MACs stored in ASCII */ |
| ethmac1: mac-address@0 { |
| reg = <0x0 0xc>; |
| }; |
| |
| ethmac2: mac-address@c { |
| reg = <0xc 0xc>; |
| }; |
| }; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| /* Debug */ |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &uart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| status = "okay"; |
| }; |
| |
| &uart4 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart4>; |
| status = "okay"; |
| }; |
| |
| &usb3_0 { |
| status = "okay"; |
| }; |
| |
| &usb3_1 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_0 { |
| dr_mode = "peripheral"; |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_1 { |
| dr_mode = "host"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| |
| /* 2.x hub on port 1 */ |
| usb_hub_2_x: hub@1 { |
| compatible = "usb5e3,610"; |
| reg = <1>; |
| reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; |
| vdd-supply = <®_vdd5v0>; |
| peer-hub = <&usb_hub_3_x>; |
| }; |
| |
| /* 3.x hub on port 2 */ |
| usb_hub_3_x: hub@2 { |
| compatible = "usb5e3,620"; |
| reg = <2>; |
| reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>; |
| vdd-supply = <®_vdd5v0>; |
| peer-hub = <&usb_hub_2_x>; |
| }; |
| }; |
| |
| &usb3_phy0 { |
| status = "okay"; |
| }; |
| |
| &usb3_phy1 { |
| status = "okay"; |
| }; |
| |
| /* µSD Card */ |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>; |
| assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; |
| assigned-clock-rates = <400000000>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| bus-width = <4>; |
| disable-wp; |
| no-sdio; |
| no-mmc; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_eqos: eqosgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 |
| MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 |
| MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 |
| MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 |
| MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 |
| MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 |
| MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 |
| MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 |
| MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f |
| MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f |
| MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f |
| MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f |
| MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f |
| MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f |
| |
| MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f |
| MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 |
| >; |
| }; |
| |
| pinctrl_fec: fecgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 |
| MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 |
| MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 |
| MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 |
| MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 |
| MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 |
| MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 |
| MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 |
| MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f |
| MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f |
| MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f |
| MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f |
| MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f |
| MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f |
| MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f |
| MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 |
| MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 |
| MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 |
| >; |
| }; |
| |
| pinctrl_flexspi0: flexspi0grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 |
| MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 |
| MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 |
| MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 |
| MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 |
| MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 |
| MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 |
| >; |
| }; |
| |
| pinctrl_i2c4: i2c4grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 |
| MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_rtc: rtcgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 |
| >; |
| }; |
| |
| pinctrl_reg_csi2_1v8: regcsi21v8grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19 |
| >; |
| }; |
| |
| pinctrl_reg_csi2_3v3: regcsi23v3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f |
| MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49 |
| MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_uart4: uart4grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49 |
| MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = < |
| MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 |
| MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 |
| MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 |
| MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| }; |
