blob: 6ab65d21861a5f360e2a65aa9128277be9a9527e [file] [log] [blame]
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Device Tree file for Marvell Armada 382 reference board
* (RD-AC3X-48G4X2XL)
*
* Copyright (C) 2020 Allied Telesis Labs
*/
/dts-v1/;
#include "armada-385.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Marvell Armada 382 RD-AC3X";
compatible = "marvell,rd-ac3x-48g4x2xl", "marvell,rd-ac3x",
"marvell,armada385", "marvell,armada380";
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &eth1;
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
};
};
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
eeprom@53 {
compatible = "atmel,24c64";
reg = <0x53>;
};
/* CPLD device present at 0x3c. Function unknown */
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
&eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
&mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
&pciec {
status = "okay";
};
&pcie1 {
/* Port 0, Lane 0 */
status = "okay";
};
&nand_controller {
status = "okay";
nand@0 {
reg = <0>;
label = "pxa3xx_nand-0";
nand-rb = <0>;
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
reg = <0x00000000 0x00500000>;
label = "u-boot";
};
partition@500000 {
reg = <0x00500000 0x00400000>;
label = "u-boot env";
};
partition@900000 {
reg = <0x00900000 0x3F700000>;
label = "user";
};
};
};
};
&refclk {
clock-frequency = <200000000>;
};