| // SPDX-License-Identifier: (GPL-2.0-or-later OR X11) |
| /* |
| * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, |
| * D-82229 Seefeld, Germany. |
| * Author: Alexander Stein |
| */ |
| |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/leds/common.h> |
| #include <dt-bindings/net/ti-dp83867.h> |
| |
| / { |
| adc { |
| compatible = "iio-hwmon"; |
| io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>; |
| }; |
| |
| aliases { |
| rtc0 = &pcf85063; |
| rtc1 = &rtc; |
| }; |
| |
| backlight_lvds: backlight-lvds { |
| compatible = "pwm-backlight"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_bl_lvds>; |
| pwms = <&adma_pwm 0 5000000 0>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <7>; |
| power-supply = <®_12v0>; |
| enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>; |
| status = "disabled"; |
| }; |
| |
| chosen { |
| stdout-path = &lpuart1; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_gpiobuttons>; |
| autorepeat; |
| |
| switch-a { |
| label = "switcha"; |
| linux,code = <BTN_0>; |
| gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>; |
| }; |
| |
| switch-b { |
| label = "switchb"; |
| linux,code = <BTN_1>; |
| gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| gpio-leds { |
| compatible = "gpio-leds"; |
| |
| led1 { |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_STATUS; |
| gpios = <&expander 1 GPIO_ACTIVE_HIGH>; |
| linux,default-trigger = "default-on"; |
| }; |
| |
| led2 { |
| color = <LED_COLOR_ID_GREEN>; |
| function = LED_FUNCTION_HEARTBEAT; |
| gpios = <&expander 2 GPIO_ACTIVE_HIGH>; |
| linux,default-trigger = "heartbeat"; |
| }; |
| }; |
| |
| /* TODO LVDS panels */ |
| |
| reg_12v0: regulator-12v0 { |
| compatible = "regulator-fixed"; |
| regulator-name = "V_12V"; |
| regulator-min-microvolt = <12000000>; |
| regulator-max-microvolt = <12000000>; |
| gpio = <&expander 6 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_pcie_1v5: regulator-pcie-1v5 { |
| compatible = "regulator-fixed"; |
| regulator-name = "MBA8XX_PCIE_1V5"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_pcie_1v5>; |
| regulator-min-microvolt = <1500000>; |
| regulator-max-microvolt = <1500000>; |
| gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>; |
| startup-delay-us = <1000>; |
| enable-active-high; |
| }; |
| |
| reg_pcie_3v3: regulator-pcie-3v3 { |
| compatible = "regulator-fixed"; |
| regulator-name = "MBA8XX_PCIE_3V3"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_pcie_3v3>; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; |
| startup-delay-us = <1000>; |
| enable-active-high; |
| regulator-always-on; |
| }; |
| |
| reg_3v3_mb: regulator-usdhc2-vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "V_3V3_MB"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| sound { |
| compatible = "fsl,imx-audio-tlv320aic32x4"; |
| model = "tqm-tlv320aic32"; |
| audio-codec = <&tlv320aic3x04>; |
| ssi-controller = <&sai1>; |
| }; |
| }; |
| |
| &adc0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_adc0>; |
| vref-supply = <®_1v8>; |
| #io-channel-cells = <1>; |
| status = "okay"; |
| }; |
| |
| &adma_pwm { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_admapwm>; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ethphy0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,dp83867-rxctrl-strap-quirk; |
| ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; |
| reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <500000>; |
| reset-deassert-us = <50000>; |
| enet-phy-lane-no-swap; |
| interrupt-parent = <&lsio_gpio3>; |
| interrupts = <0 IRQ_TYPE_EDGE_FALLING>; |
| }; |
| |
| ethphy3: ethernet-phy@3 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <3>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ethphy3>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,dp83867-rxctrl-strap-quirk; |
| ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; |
| reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>; |
| reset-assert-us = <500000>; |
| reset-deassert-us = <50000>; |
| enet-phy-lane-no-swap; |
| interrupt-parent = <&lsio_gpio3>; |
| interrupts = <1 IRQ_TYPE_EDGE_FALLING>; |
| }; |
| }; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec2>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy3>; |
| status = "okay"; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_can0>; |
| xceiver-supply = <®_3v3>; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_can1>; |
| xceiver-supply = <®_3v3>; |
| status = "okay"; |
| }; |
| |
| &i2c1 { |
| tlv320aic3x04: audio-codec@18 { |
| compatible = "ti,tlv320aic32x4"; |
| reg = <0x18>; |
| clocks = <&mclkout0_lpcg 0>; |
| clock-names = "mclk"; |
| iov-supply = <®_1v8>; |
| ldoin-supply = <®_3v3>; |
| }; |
| |
| se97b_1c: temperature-sensor@1c { |
| compatible = "nxp,se97b", "jedec,jc-42.4-temp"; |
| reg = <0x1c>; |
| }; |
| |
| at24c02_54: eeprom@54 { |
| compatible = "nxp,se97b", "atmel,24c02"; |
| reg = <0x54>; |
| pagesize = <16>; |
| vcc-supply = <®_3v3>; |
| }; |
| |
| expander: gpio@70 { |
| compatible = "nxp,pca9538"; |
| reg = <0x70>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pca9538>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&lsio_gpio4>; |
| interrupts = <19 IRQ_TYPE_LEVEL_LOW>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| vcc-supply = <®_1v8>; |
| |
| gpio-line-names = "", "LED_A", |
| "LED_B", "", |
| "DSI_EN", "USB_RESET#", |
| "V_12V_EN", "PCIE_DIS#"; |
| }; |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "gpio"; |
| pinctrl-0 = <&pinctrl_lpi2c2>; |
| pinctrl-1 = <&pinctrl_lpi2c2gpio>; |
| scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; |
| status = "okay"; |
| }; |
| |
| /* TODO LDB */ |
| |
| &lpspi1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi1>; |
| cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &lpspi2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi2>; |
| cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &lpspi3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi3>; |
| num-cs = <2>; |
| cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| }; |
| |
| &lpuart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart1>; |
| status = "okay"; |
| }; |
| |
| &lpuart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart3>; |
| status = "okay"; |
| }; |
| |
| &lsio_gpio3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lsgpio3>; |
| gpio-line-names = "", "", "", "", |
| "", "", "", "", |
| "", "", "", "", |
| "", "", "", "X4_15", |
| "", "", "", "", |
| "", "", "", "", |
| "", "", "", "", |
| "", "", "", ""; |
| }; |
| |
| /* TODO: Mini-PCIe */ |
| |
| &sai1 { |
| assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, |
| <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, |
| <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, |
| <&sai1_lpcg 0>; |
| assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai1>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg1>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| power-active-high; |
| over-current-active-low; |
| dr_mode = "otg"; |
| status = "okay"; |
| }; |
| |
| &usbotg3 { |
| status = "okay"; |
| }; |
| |
| &usbotg3_cdns3 { |
| dr_mode = "host"; |
| status = "okay"; |
| }; |
| |
| &usbphy1 { |
| status = "okay"; |
| }; |
| |
| &usb3_phy { |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>; |
| vmmc-supply = <®_3v3_mb>; |
| no-1-8-v; |
| no-sdio; |
| no-mmc; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl_adc0: adc0grp { |
| fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>, |
| <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>, |
| <IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>, |
| <IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>; |
| }; |
| |
| pinctrl_admapwm: admapwmgrp { |
| fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>; |
| }; |
| |
| pinctrl_bl_lvds: bllvdsgrp { |
| fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>; |
| }; |
| |
| pinctrl_can0: can0grp { |
| fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>, |
| <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>; |
| }; |
| |
| pinctrl_can1: can1grp { |
| fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>, |
| <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>; |
| }; |
| |
| pinctrl_ethphy0: ethphy0grp { |
| fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>, |
| <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>; |
| }; |
| |
| pinctrl_ethphy3: ethphy3grp { |
| fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>, |
| <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>, |
| <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>, |
| <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>, |
| <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>; |
| }; |
| |
| pinctrl_fec2: fec2grp { |
| fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>, |
| <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>, |
| <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>, |
| <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>, |
| <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>, |
| <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>, |
| <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>, |
| <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>, |
| <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>, |
| <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>, |
| <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>, |
| <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>; |
| }; |
| |
| pinctrl_gpiobuttons: gpiobuttonsgrp { |
| fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>, |
| <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>; |
| }; |
| |
| pinctrl_lpi2c2: lpi2c2grp { |
| fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>, |
| <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>; |
| }; |
| |
| pinctrl_lpi2c2gpio: lpi2c2gpiogrp { |
| fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>, |
| <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>; |
| }; |
| |
| pinctrl_lpuart1: lpuart1grp { |
| fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>, |
| <IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>; |
| }; |
| |
| pinctrl_lpuart3: lpuart3grp { |
| fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, |
| <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; |
| }; |
| |
| pinctrl_lsgpio3: lsgpio3grp { |
| fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>; |
| }; |
| |
| pinctrl_pca9538: pca9538grp { |
| fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>; |
| }; |
| |
| pinctrl_pcieb: pcieagrp { |
| fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>, |
| <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>, |
| <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>; |
| }; |
| |
| pinctrl_reg_pcie_1v5: regpcie1v5grp { |
| fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>; |
| }; |
| |
| pinctrl_reg_pcie_3v3: regpcie3v3grp { |
| fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>; |
| }; |
| |
| pinctrl_sai1: sai1grp { |
| fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>, |
| <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>, |
| <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>, |
| <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>, |
| <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>; |
| }; |
| |
| pinctrl_spi1: spi1grp { |
| fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>, |
| <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>, |
| <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>, |
| <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>, |
| <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>; |
| }; |
| |
| pinctrl_spi2: spi2grp { |
| fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>, |
| <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>, |
| <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>, |
| <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>; |
| }; |
| |
| pinctrl_spi3: spi3grp { |
| fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>, |
| <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>, |
| <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>, |
| <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>, |
| <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>; |
| }; |
| |
| pinctrl_usbotg1: usbotg1grp { |
| fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>, |
| <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2gpiogrp { |
| fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>, |
| <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, |
| <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>, |
| <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>, |
| <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>, |
| <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>, |
| <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>, |
| <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { |
| fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, |
| <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, |
| <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, |
| <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, |
| <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, |
| <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, |
| <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { |
| fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>, |
| <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>, |
| <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>, |
| <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>, |
| <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>, |
| <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>, |
| <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>; |
| }; |
| }; |
