| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /** |
| * DT Overlay for CPSW9G in RGMII mode using J7 GESI EXP BRD board with |
| * J721E board. |
| * |
| * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM |
| * |
| * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| /dts-v1/; |
| /plugin/; |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/net/ti-dp83867.h> |
| |
| #include "k3-pinctrl.h" |
| |
| &{/} { |
| aliases { |
| ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; |
| ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; |
| ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; |
| ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; |
| }; |
| }; |
| |
| &cpsw0 { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&rgmii1_default_pins |
| &rgmii2_default_pins |
| &rgmii3_default_pins |
| &rgmii4_default_pins>; |
| }; |
| |
| &cpsw0_port1 { |
| status = "okay"; |
| phy-handle = <&cpsw9g_phy12>; |
| phy-mode = "rgmii-rxid"; |
| mac-address = [00 00 00 00 00 00]; |
| phys = <&cpsw0_phy_gmii_sel 1>; |
| }; |
| |
| &cpsw0_port2 { |
| status = "okay"; |
| phy-handle = <&cpsw9g_phy15>; |
| phy-mode = "rgmii-rxid"; |
| mac-address = [00 00 00 00 00 00]; |
| phys = <&cpsw0_phy_gmii_sel 2>; |
| }; |
| |
| &cpsw0_port3 { |
| status = "okay"; |
| phy-handle = <&cpsw9g_phy0>; |
| phy-mode = "rgmii-rxid"; |
| mac-address = [00 00 00 00 00 00]; |
| phys = <&cpsw0_phy_gmii_sel 3>; |
| }; |
| |
| &cpsw0_port4 { |
| status = "okay"; |
| phy-handle = <&cpsw9g_phy3>; |
| phy-mode = "rgmii-rxid"; |
| mac-address = [00 00 00 00 00 00]; |
| phys = <&cpsw0_phy_gmii_sel 4>; |
| }; |
| |
| &cpsw9g_mdio { |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mdio0_default_pins>; |
| bus_freq = <1000000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpsw9g_phy0: ethernet-phy@0 { |
| reg = <0>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| }; |
| cpsw9g_phy3: ethernet-phy@3 { |
| reg = <3>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| }; |
| cpsw9g_phy12: ethernet-phy@12 { |
| reg = <12>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| }; |
| cpsw9g_phy15: ethernet-phy@15 { |
| reg = <15>; |
| ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; |
| ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
| ti,min-output-impedance; |
| }; |
| }; |
| |
| &exp1 { |
| p15-hog { |
| /* P15 - EXP_MUX2 */ |
| gpio-hog; |
| gpios = <13 GPIO_ACTIVE_HIGH>; |
| output-high; |
| line-name = "EXP_MUX2"; |
| }; |
| |
| p16-hog { |
| /* P16 - EXP_MUX3 */ |
| gpio-hog; |
| gpios = <14 GPIO_ACTIVE_HIGH>; |
| output-high; |
| line-name = "EXP_MUX3"; |
| }; |
| }; |
| |
| &main_pmx0 { |
| mdio0_default_pins: mdio0-default-pins { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ |
| J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ |
| >; |
| }; |
| |
| rgmii1_default_pins: rgmii1-default-pins { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */ |
| J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */ |
| J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */ |
| J721E_IOPAD(0x10, PIN_INPUT, 4) /* (AJ23) PRG1_PRU0_GPO3.RGMII1_RD3 */ |
| J721E_IOPAD(0x1c, PIN_INPUT, 4) /* (AD22) PRG1_PRU0_GPO6.RGMII1_RXC */ |
| J721E_IOPAD(0x14, PIN_INPUT, 4) /* (AH23) PRG1_PRU0_GPO4.RGMII1_RX_CTL */ |
| J721E_IOPAD(0x30, PIN_OUTPUT, 4) /* (AF24) PRG1_PRU0_GPO11.RGMII1_TD0 */ |
| J721E_IOPAD(0x34, PIN_OUTPUT, 4) /* (AJ24) PRG1_PRU0_GPO12.RGMII1_TD1 */ |
| J721E_IOPAD(0x38, PIN_OUTPUT, 4) /* (AG24) PRG1_PRU0_GPO13.RGMII1_TD2 */ |
| J721E_IOPAD(0x3c, PIN_OUTPUT, 4) /* (AD24) PRG1_PRU0_GPO14.RGMII1_TD3 */ |
| J721E_IOPAD(0x44, PIN_OUTPUT, 4) /* (AE24) PRG1_PRU0_GPO16.RGMII1_TXC */ |
| J721E_IOPAD(0x40, PIN_OUTPUT, 4) /* (AC24) PRG1_PRU0_GPO15.RGMII1_TX_CTL */ |
| >; |
| }; |
| |
| rgmii2_default_pins: rgmii2-default-pins { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x58, PIN_INPUT, 4) /* (AE22) PRG1_PRU1_GPO0.RGMII2_RD0 */ |
| J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (AG23) PRG1_PRU1_GPO1.RGMII2_RD1 */ |
| J721E_IOPAD(0x60, PIN_INPUT, 4) /* (AF23) PRG1_PRU1_GPO2.RGMII2_RD2 */ |
| J721E_IOPAD(0x64, PIN_INPUT, 4) /* (AD23) PRG1_PRU1_GPO3.RGMII2_RD3 */ |
| J721E_IOPAD(0x70, PIN_INPUT, 4) /* (AE23) PRG1_PRU1_GPO6.RGMII2_RXC */ |
| J721E_IOPAD(0x68, PIN_INPUT, 4) /* (AH24) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ |
| J721E_IOPAD(0x84, PIN_OUTPUT, 4) /* (AJ25) PRG1_PRU1_GPO11.RGMII2_TD0 */ |
| J721E_IOPAD(0x88, PIN_OUTPUT, 4) /* (AH25) PRG1_PRU1_GPO12.RGMII2_TD1 */ |
| J721E_IOPAD(0x8c, PIN_OUTPUT, 4) /* (AG25) PRG1_PRU1_GPO13.RGMII2_TD2 */ |
| J721E_IOPAD(0x90, PIN_OUTPUT, 4) /* (AH26) PRG1_PRU1_GPO14.RGMII2_TD3 */ |
| J721E_IOPAD(0x98, PIN_OUTPUT, 4) /* (AJ26) PRG1_PRU1_GPO16.RGMII2_TXC */ |
| J721E_IOPAD(0x94, PIN_OUTPUT, 4) /* (AJ27) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ |
| >; |
| }; |
| |
| rgmii3_default_pins: rgmii3-default-pins { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0xb0, PIN_INPUT, 4) /* (AF28) PRG0_PRU0_GPO0.RGMII3_RD0 */ |
| J721E_IOPAD(0xb4, PIN_INPUT, 4) /* (AE28) PRG0_PRU0_GPO1.RGMII3_RD1 */ |
| J721E_IOPAD(0xb8, PIN_INPUT, 4) /* (AE27) PRG0_PRU0_GPO2.RGMII3_RD2 */ |
| J721E_IOPAD(0xbc, PIN_INPUT, 4) /* (AD26) PRG0_PRU0_GPO3.RGMII3_RD3 */ |
| J721E_IOPAD(0xc8, PIN_INPUT, 4) /* (AE26) PRG0_PRU0_GPO6.RGMII3_RXC */ |
| J721E_IOPAD(0xc0, PIN_INPUT, 4) /* (AD25) PRG0_PRU0_GPO4.RGMII3_RX_CTL */ |
| J721E_IOPAD(0xdc, PIN_OUTPUT, 4) /* (AJ28) PRG0_PRU0_GPO11.RGMII3_TD0 */ |
| J721E_IOPAD(0xe0, PIN_OUTPUT, 4) /* (AH27) PRG0_PRU0_GPO12.RGMII3_TD1 */ |
| J721E_IOPAD(0xe4, PIN_OUTPUT, 4) /* (AH29) PRG0_PRU0_GPO13.RGMII3_TD2 */ |
| J721E_IOPAD(0xe8, PIN_OUTPUT, 4) /* (AG28) PRG0_PRU0_GPO14.RGMII3_TD3 */ |
| J721E_IOPAD(0xf0, PIN_OUTPUT, 4) /* (AH28) PRG0_PRU0_GPO16.RGMII3_TXC */ |
| J721E_IOPAD(0xec, PIN_OUTPUT, 4) /* (AG27) PRG0_PRU0_GPO15.RGMII3_TX_CTL */ |
| >; |
| }; |
| |
| rgmii4_default_pins: rgmii4-default-pins { |
| pinctrl-single,pins = < |
| J721E_IOPAD(0x100, PIN_INPUT, 4) /* (AE29) PRG0_PRU1_GPO0.RGMII4_RD0 */ |
| J721E_IOPAD(0x104, PIN_INPUT, 4) /* (AD28) PRG0_PRU1_GPO1.RGMII4_RD1 */ |
| J721E_IOPAD(0x108, PIN_INPUT, 4) /* (AD27) PRG0_PRU1_GPO2.RGMII4_RD2 */ |
| J721E_IOPAD(0x10c, PIN_INPUT, 4) /* (AC25) PRG0_PRU1_GPO3.RGMII4_RD3 */ |
| J721E_IOPAD(0x118, PIN_INPUT, 4) /* (AC26) PRG0_PRU1_GPO6.RGMII4_RXC */ |
| J721E_IOPAD(0x110, PIN_INPUT, 4) /* (AD29) PRG0_PRU1_GPO4.RGMII4_RX_CTL */ |
| J721E_IOPAD(0x12c, PIN_OUTPUT, 4) /* (AG26) PRG0_PRU1_GPO11.RGMII4_TD0 */ |
| J721E_IOPAD(0x130, PIN_OUTPUT, 4) /* (AF27) PRG0_PRU1_GPO12.RGMII4_TD1 */ |
| J721E_IOPAD(0x134, PIN_OUTPUT, 4) /* (AF26) PRG0_PRU1_GPO13.RGMII4_TD2 */ |
| J721E_IOPAD(0x138, PIN_OUTPUT, 4) /* (AE25) PRG0_PRU1_GPO14.RGMII4_TD3 */ |
| J721E_IOPAD(0x140, PIN_OUTPUT, 4) /* (AG29) PRG0_PRU1_GPO16.RGMII4_TXC */ |
| J721E_IOPAD(0x13c, PIN_OUTPUT, 4) /* (AF29) PRG0_PRU1_GPO15.RGMII4_TX_CTL */ |
| >; |
| }; |
| }; |
