blob: 47bb5480b5b0064de76c06152e9687c10d1f626a [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0-only OR MIT
/**
* DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2
* on J721E SK, AM68 SK or AM69-SK board.
* https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf
*
* Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "k3-pinctrl.h"
&{/} {
clk_imx219_fixed: imx219-xclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
};
&csi_mux {
idle-state = <1>;
};
/* CAM0 I2C */
&cam0_i2c {
#address-cells = <1>;
#size-cells = <0>;
imx219_0: imx219-0@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&clk_imx219_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2rx0_in_sensor>;
link-frequencies = /bits/ 64 <456000000>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
/* CAM1 I2C */
&cam1_i2c {
#address-cells = <1>;
#size-cells = <0>;
imx219_1: imx219-1@10 {
compatible = "sony,imx219";
reg = <0x10>;
clocks = <&clk_imx219_fixed>;
clock-names = "xclk";
port {
csi2_cam1: endpoint {
remote-endpoint = <&csi2rx1_in_sensor>;
link-frequencies = /bits/ 64 <456000000>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&cdns_csi2rx0 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi0_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx0_in_sensor: endpoint {
remote-endpoint = <&csi2_cam0>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
csi0_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi0_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi0_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi0_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
&dphy0 {
status = "okay";
};
&ti_csi2rx0 {
status = "okay";
};
&cdns_csi2rx1 {
ports {
#address-cells = <1>;
#size-cells = <0>;
csi1_port0: port@0 {
reg = <0>;
status = "okay";
csi2rx1_in_sensor: endpoint {
remote-endpoint = <&csi2_cam1>;
bus-type = <4>; /* CSI2 DPHY. */
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
csi1_port1: port@1 {
reg = <1>;
status = "disabled";
};
csi1_port2: port@2 {
reg = <2>;
status = "disabled";
};
csi1_port3: port@3 {
reg = <3>;
status = "disabled";
};
csi1_port4: port@4 {
reg = <4>;
status = "disabled";
};
};
};
&dphy1 {
status = "okay";
};
&ti_csi2rx1 {
status = "okay";
};