Documentation/devicetree/bindings/media/cedrus.txt

Device-tree bindings for the VPU found in Allwinner SoCs, referred to as the
Video Engine (VE) in Allwinner literature.

The VPU can only access the first 256 MiB of DRAM, that are DMA-mapped starting
from the DRAM base. This requires specific memory allocation and handling.

Required properties:
- compatible		: must be one of the following compatibles:
			- "allwinner,sun4i-a10-video-engine"
			- "allwinner,sun5i-a13-video-engine"
			- "allwinner,sun7i-a20-video-engine"
			- "allwinner,sun8i-a33-video-engine"
			- "allwinner,sun8i-h3-video-engine"
- reg			: register base and length of VE;
- clocks		: list of clock specifiers, corresponding to entries in
			  the clock-names property;
- clock-names		: should contain "ahb", "mod" and "ram" entries;
- resets		: phandle for reset;
- interrupts		: VE interrupt number;
- allwinner,sram	: SRAM region to use with the VE.

Optional properties:
- memory-region		: CMA pool to use for buffers allocation instead of the
			  default CMA pool.

Example:

reserved-memory {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges;

	/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
	cma_pool: cma@4a000000 {
		compatible = "shared-dma-pool";
		size = <0x6000000>;
		alloc-ranges = <0x4a000000 0x6000000>;
		reusable;
		linux,cma-default;
	};
};

video-codec@1c0e000 {
	compatible = "allwinner,sun7i-a20-video-engine";
	reg = <0x01c0e000 0x1000>;

	clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
		 <&ccu CLK_DRAM_VE>;
	clock-names = "ahb", "mod", "ram";

	resets = <&ccu RST_VE>;
	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	allwinner,sram = <&ve_sram 1>;
};