| /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ |
| /* Copyright (c) 2023 Imagination Technologies Ltd. */ |
| |
| /* *** Autogenerated C -- do not edit *** */ |
| |
| #ifndef PVR_ROGUE_CR_DEFS_H |
| #define PVR_ROGUE_CR_DEFS_H |
| |
| /* clang-format off */ |
| |
| #define ROGUE_CR_DEFS_REVISION 1 |
| |
| /* Register ROGUE_CR_RASTERISATION_INDIRECT */ |
| #define ROGUE_CR_RASTERISATION_INDIRECT 0x8238U |
| #define ROGUE_CR_RASTERISATION_INDIRECT_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_RASTERISATION_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_PBE_INDIRECT */ |
| #define ROGUE_CR_PBE_INDIRECT 0x83E0U |
| #define ROGUE_CR_PBE_INDIRECT_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_PBE_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_PBE_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_PBE_PERF_INDIRECT */ |
| #define ROGUE_CR_PBE_PERF_INDIRECT 0x83D8U |
| #define ROGUE_CR_PBE_PERF_INDIRECT_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_PBE_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_TPU_PERF_INDIRECT */ |
| #define ROGUE_CR_TPU_PERF_INDIRECT 0x83F0U |
| #define ROGUE_CR_TPU_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_TPU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U |
| |
| /* Register ROGUE_CR_RASTERISATION_PERF_INDIRECT */ |
| #define ROGUE_CR_RASTERISATION_PERF_INDIRECT 0x8318U |
| #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_RASTERISATION_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT */ |
| #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT 0x8028U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U |
| |
| /* Register ROGUE_CR_USC_PERF_INDIRECT */ |
| #define ROGUE_CR_USC_PERF_INDIRECT 0x8030U |
| #define ROGUE_CR_USC_PERF_INDIRECT_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_USC_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_BLACKPEARL_INDIRECT */ |
| #define ROGUE_CR_BLACKPEARL_INDIRECT 0x8388U |
| #define ROGUE_CR_BLACKPEARL_INDIRECT_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BLACKPEARL_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_BLACKPEARL_PERF_INDIRECT */ |
| #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT 0x83F8U |
| #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BLACKPEARL_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_TEXAS3_PERF_INDIRECT */ |
| #define ROGUE_CR_TEXAS3_PERF_INDIRECT 0x83D0U |
| #define ROGUE_CR_TEXAS3_PERF_INDIRECT_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_TEXAS3_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFF8U |
| |
| /* Register ROGUE_CR_TEXAS_PERF_INDIRECT */ |
| #define ROGUE_CR_TEXAS_PERF_INDIRECT 0x8288U |
| #define ROGUE_CR_TEXAS_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_TEXAS_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_BX_TU_PERF_INDIRECT */ |
| #define ROGUE_CR_BX_TU_PERF_INDIRECT 0xC900U |
| #define ROGUE_CR_BX_TU_PERF_INDIRECT_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BX_TU_PERF_INDIRECT_ADDRESS_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_CLK_CTRL */ |
| #define ROGUE_CR_CLK_CTRL 0x0000U |
| #define ROGUE_CR_CLK_CTRL__PBE2_XE__MASKFULL 0xFFFFFF003F3FFFFFULL |
| #define ROGUE_CR_CLK_CTRL__S7_TOP__MASKFULL 0xCFCF03000F3F3F0FULL |
| #define ROGUE_CR_CLK_CTRL_MASKFULL 0xFFFFFF003F3FFFFFULL |
| #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_SHIFT 62U |
| #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_CLRMSK 0x3FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_ON 0x4000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_TEXAS_AUTO 0x8000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_IPP_SHIFT 60U |
| #define ROGUE_CR_CLK_CTRL_IPP_CLRMSK 0xCFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_IPP_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_IPP_ON 0x1000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_IPP_AUTO 0x2000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBC_SHIFT 58U |
| #define ROGUE_CR_CLK_CTRL_FBC_CLRMSK 0xF3FFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_FBC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBC_ON 0x0400000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBC_AUTO 0x0800000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBDC_SHIFT 56U |
| #define ROGUE_CR_CLK_CTRL_FBDC_CLRMSK 0xFCFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_FBDC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBDC_ON 0x0100000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FBDC_AUTO 0x0200000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_SHIFT 54U |
| #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_CLRMSK 0xFF3FFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_ON 0x0040000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_FB_TLCACHE_AUTO 0x0080000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_USCS_SHIFT 52U |
| #define ROGUE_CR_CLK_CTRL_USCS_CLRMSK 0xFFCFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_USCS_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_USCS_ON 0x0010000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_USCS_AUTO 0x0020000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_PBE_SHIFT 50U |
| #define ROGUE_CR_CLK_CTRL_PBE_CLRMSK 0xFFF3FFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_PBE_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_PBE_ON 0x0004000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_PBE_AUTO 0x0008000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L1_SHIFT 48U |
| #define ROGUE_CR_CLK_CTRL_MCU_L1_CLRMSK 0xFFFCFFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L1_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L1_ON 0x0001000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L1_AUTO 0x0002000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_CDM_SHIFT 46U |
| #define ROGUE_CR_CLK_CTRL_CDM_CLRMSK 0xFFFF3FFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_CDM_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_CDM_ON 0x0000400000000000ULL |
| #define ROGUE_CR_CLK_CTRL_CDM_AUTO 0x0000800000000000ULL |
| #define ROGUE_CR_CLK_CTRL_SIDEKICK_SHIFT 44U |
| #define ROGUE_CR_CLK_CTRL_SIDEKICK_CLRMSK 0xFFFFCFFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_SIDEKICK_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_SIDEKICK_ON 0x0000100000000000ULL |
| #define ROGUE_CR_CLK_CTRL_SIDEKICK_AUTO 0x0000200000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_SHIFT 42U |
| #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_CLRMSK 0xFFFFF3FFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_ON 0x0000040000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_SIDEKICK_AUTO 0x0000080000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_SHIFT 40U |
| #define ROGUE_CR_CLK_CTRL_BIF_CLRMSK 0xFFFFFCFFFFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_BIF_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_ON 0x0000010000000000ULL |
| #define ROGUE_CR_CLK_CTRL_BIF_AUTO 0x0000020000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_SHIFT 28U |
| #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFCFFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_ON 0x0000000010000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_MCU_DEMUX_AUTO 0x0000000020000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L0_SHIFT 26U |
| #define ROGUE_CR_CLK_CTRL_MCU_L0_CLRMSK 0xFFFFFFFFF3FFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L0_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L0_ON 0x0000000004000000ULL |
| #define ROGUE_CR_CLK_CTRL_MCU_L0_AUTO 0x0000000008000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_SHIFT 24U |
| #define ROGUE_CR_CLK_CTRL_TPU_CLRMSK 0xFFFFFFFFFCFFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_TPU_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_ON 0x0000000001000000ULL |
| #define ROGUE_CR_CLK_CTRL_TPU_AUTO 0x0000000002000000ULL |
| #define ROGUE_CR_CLK_CTRL_USC_SHIFT 20U |
| #define ROGUE_CR_CLK_CTRL_USC_CLRMSK 0xFFFFFFFFFFCFFFFFULL |
| #define ROGUE_CR_CLK_CTRL_USC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_USC_ON 0x0000000000100000ULL |
| #define ROGUE_CR_CLK_CTRL_USC_AUTO 0x0000000000200000ULL |
| #define ROGUE_CR_CLK_CTRL_TLA_SHIFT 18U |
| #define ROGUE_CR_CLK_CTRL_TLA_CLRMSK 0xFFFFFFFFFFF3FFFFULL |
| #define ROGUE_CR_CLK_CTRL_TLA_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TLA_ON 0x0000000000040000ULL |
| #define ROGUE_CR_CLK_CTRL_TLA_AUTO 0x0000000000080000ULL |
| #define ROGUE_CR_CLK_CTRL_SLC_SHIFT 16U |
| #define ROGUE_CR_CLK_CTRL_SLC_CLRMSK 0xFFFFFFFFFFFCFFFFULL |
| #define ROGUE_CR_CLK_CTRL_SLC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_SLC_ON 0x0000000000010000ULL |
| #define ROGUE_CR_CLK_CTRL_SLC_AUTO 0x0000000000020000ULL |
| #define ROGUE_CR_CLK_CTRL_UVS_SHIFT 14U |
| #define ROGUE_CR_CLK_CTRL_UVS_CLRMSK 0xFFFFFFFFFFFF3FFFULL |
| #define ROGUE_CR_CLK_CTRL_UVS_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_UVS_ON 0x0000000000004000ULL |
| #define ROGUE_CR_CLK_CTRL_UVS_AUTO 0x0000000000008000ULL |
| #define ROGUE_CR_CLK_CTRL_PDS_SHIFT 12U |
| #define ROGUE_CR_CLK_CTRL_PDS_CLRMSK 0xFFFFFFFFFFFFCFFFULL |
| #define ROGUE_CR_CLK_CTRL_PDS_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_PDS_ON 0x0000000000001000ULL |
| #define ROGUE_CR_CLK_CTRL_PDS_AUTO 0x0000000000002000ULL |
| #define ROGUE_CR_CLK_CTRL_VDM_SHIFT 10U |
| #define ROGUE_CR_CLK_CTRL_VDM_CLRMSK 0xFFFFFFFFFFFFF3FFULL |
| #define ROGUE_CR_CLK_CTRL_VDM_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_VDM_ON 0x0000000000000400ULL |
| #define ROGUE_CR_CLK_CTRL_VDM_AUTO 0x0000000000000800ULL |
| #define ROGUE_CR_CLK_CTRL_PM_SHIFT 8U |
| #define ROGUE_CR_CLK_CTRL_PM_CLRMSK 0xFFFFFFFFFFFFFCFFULL |
| #define ROGUE_CR_CLK_CTRL_PM_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_PM_ON 0x0000000000000100ULL |
| #define ROGUE_CR_CLK_CTRL_PM_AUTO 0x0000000000000200ULL |
| #define ROGUE_CR_CLK_CTRL_GPP_SHIFT 6U |
| #define ROGUE_CR_CLK_CTRL_GPP_CLRMSK 0xFFFFFFFFFFFFFF3FULL |
| #define ROGUE_CR_CLK_CTRL_GPP_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_GPP_ON 0x0000000000000040ULL |
| #define ROGUE_CR_CLK_CTRL_GPP_AUTO 0x0000000000000080ULL |
| #define ROGUE_CR_CLK_CTRL_TE_SHIFT 4U |
| #define ROGUE_CR_CLK_CTRL_TE_CLRMSK 0xFFFFFFFFFFFFFFCFULL |
| #define ROGUE_CR_CLK_CTRL_TE_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TE_ON 0x0000000000000010ULL |
| #define ROGUE_CR_CLK_CTRL_TE_AUTO 0x0000000000000020ULL |
| #define ROGUE_CR_CLK_CTRL_TSP_SHIFT 2U |
| #define ROGUE_CR_CLK_CTRL_TSP_CLRMSK 0xFFFFFFFFFFFFFFF3ULL |
| #define ROGUE_CR_CLK_CTRL_TSP_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_TSP_ON 0x0000000000000004ULL |
| #define ROGUE_CR_CLK_CTRL_TSP_AUTO 0x0000000000000008ULL |
| #define ROGUE_CR_CLK_CTRL_ISP_SHIFT 0U |
| #define ROGUE_CR_CLK_CTRL_ISP_CLRMSK 0xFFFFFFFFFFFFFFFCULL |
| #define ROGUE_CR_CLK_CTRL_ISP_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL_ISP_ON 0x0000000000000001ULL |
| #define ROGUE_CR_CLK_CTRL_ISP_AUTO 0x0000000000000002ULL |
| |
| /* Register ROGUE_CR_CLK_STATUS */ |
| #define ROGUE_CR_CLK_STATUS 0x0008U |
| #define ROGUE_CR_CLK_STATUS__PBE2_XE__MASKFULL 0x00000001FFF077FFULL |
| #define ROGUE_CR_CLK_STATUS__S7_TOP__MASKFULL 0x00000001B3101773ULL |
| #define ROGUE_CR_CLK_STATUS_MASKFULL 0x00000001FFF077FFULL |
| #define ROGUE_CR_CLK_STATUS_MCU_FBTC_SHIFT 32U |
| #define ROGUE_CR_CLK_STATUS_MCU_FBTC_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_MCU_FBTC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_MCU_FBTC_RUNNING 0x0000000100000000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_SHIFT 31U |
| #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_TEXAS_RUNNING 0x0000000080000000ULL |
| #define ROGUE_CR_CLK_STATUS_IPP_SHIFT 30U |
| #define ROGUE_CR_CLK_STATUS_IPP_CLRMSK 0xFFFFFFFFBFFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_IPP_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_IPP_RUNNING 0x0000000040000000ULL |
| #define ROGUE_CR_CLK_STATUS_FBC_SHIFT 29U |
| #define ROGUE_CR_CLK_STATUS_FBC_CLRMSK 0xFFFFFFFFDFFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_FBC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_FBC_RUNNING 0x0000000020000000ULL |
| #define ROGUE_CR_CLK_STATUS_FBDC_SHIFT 28U |
| #define ROGUE_CR_CLK_STATUS_FBDC_CLRMSK 0xFFFFFFFFEFFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_FBDC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_FBDC_RUNNING 0x0000000010000000ULL |
| #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_SHIFT 27U |
| #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_CLRMSK 0xFFFFFFFFF7FFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_FB_TLCACHE_RUNNING 0x0000000008000000ULL |
| #define ROGUE_CR_CLK_STATUS_USCS_SHIFT 26U |
| #define ROGUE_CR_CLK_STATUS_USCS_CLRMSK 0xFFFFFFFFFBFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_USCS_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_USCS_RUNNING 0x0000000004000000ULL |
| #define ROGUE_CR_CLK_STATUS_PBE_SHIFT 25U |
| #define ROGUE_CR_CLK_STATUS_PBE_CLRMSK 0xFFFFFFFFFDFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_PBE_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_PBE_RUNNING 0x0000000002000000ULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L1_SHIFT 24U |
| #define ROGUE_CR_CLK_STATUS_MCU_L1_CLRMSK 0xFFFFFFFFFEFFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L1_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L1_RUNNING 0x0000000001000000ULL |
| #define ROGUE_CR_CLK_STATUS_CDM_SHIFT 23U |
| #define ROGUE_CR_CLK_STATUS_CDM_CLRMSK 0xFFFFFFFFFF7FFFFFULL |
| #define ROGUE_CR_CLK_STATUS_CDM_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_CDM_RUNNING 0x0000000000800000ULL |
| #define ROGUE_CR_CLK_STATUS_SIDEKICK_SHIFT 22U |
| #define ROGUE_CR_CLK_STATUS_SIDEKICK_CLRMSK 0xFFFFFFFFFFBFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_SIDEKICK_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_SIDEKICK_RUNNING 0x0000000000400000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_SHIFT 21U |
| #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_SIDEKICK_RUNNING 0x0000000000200000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_SHIFT 20U |
| #define ROGUE_CR_CLK_STATUS_BIF_CLRMSK 0xFFFFFFFFFFEFFFFFULL |
| #define ROGUE_CR_CLK_STATUS_BIF_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_BIF_RUNNING 0x0000000000100000ULL |
| #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_SHIFT 14U |
| #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFBFFFULL |
| #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_TPU_MCU_DEMUX_RUNNING 0x0000000000004000ULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L0_SHIFT 13U |
| #define ROGUE_CR_CLK_STATUS_MCU_L0_CLRMSK 0xFFFFFFFFFFFFDFFFULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L0_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_MCU_L0_RUNNING 0x0000000000002000ULL |
| #define ROGUE_CR_CLK_STATUS_TPU_SHIFT 12U |
| #define ROGUE_CR_CLK_STATUS_TPU_CLRMSK 0xFFFFFFFFFFFFEFFFULL |
| #define ROGUE_CR_CLK_STATUS_TPU_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_TPU_RUNNING 0x0000000000001000ULL |
| #define ROGUE_CR_CLK_STATUS_USC_SHIFT 10U |
| #define ROGUE_CR_CLK_STATUS_USC_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_CLK_STATUS_USC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_USC_RUNNING 0x0000000000000400ULL |
| #define ROGUE_CR_CLK_STATUS_TLA_SHIFT 9U |
| #define ROGUE_CR_CLK_STATUS_TLA_CLRMSK 0xFFFFFFFFFFFFFDFFULL |
| #define ROGUE_CR_CLK_STATUS_TLA_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_TLA_RUNNING 0x0000000000000200ULL |
| #define ROGUE_CR_CLK_STATUS_SLC_SHIFT 8U |
| #define ROGUE_CR_CLK_STATUS_SLC_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_CLK_STATUS_SLC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_SLC_RUNNING 0x0000000000000100ULL |
| #define ROGUE_CR_CLK_STATUS_UVS_SHIFT 7U |
| #define ROGUE_CR_CLK_STATUS_UVS_CLRMSK 0xFFFFFFFFFFFFFF7FULL |
| #define ROGUE_CR_CLK_STATUS_UVS_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_UVS_RUNNING 0x0000000000000080ULL |
| #define ROGUE_CR_CLK_STATUS_PDS_SHIFT 6U |
| #define ROGUE_CR_CLK_STATUS_PDS_CLRMSK 0xFFFFFFFFFFFFFFBFULL |
| #define ROGUE_CR_CLK_STATUS_PDS_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_PDS_RUNNING 0x0000000000000040ULL |
| #define ROGUE_CR_CLK_STATUS_VDM_SHIFT 5U |
| #define ROGUE_CR_CLK_STATUS_VDM_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_CLK_STATUS_VDM_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_VDM_RUNNING 0x0000000000000020ULL |
| #define ROGUE_CR_CLK_STATUS_PM_SHIFT 4U |
| #define ROGUE_CR_CLK_STATUS_PM_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_CLK_STATUS_PM_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_PM_RUNNING 0x0000000000000010ULL |
| #define ROGUE_CR_CLK_STATUS_GPP_SHIFT 3U |
| #define ROGUE_CR_CLK_STATUS_GPP_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_CLK_STATUS_GPP_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_GPP_RUNNING 0x0000000000000008ULL |
| #define ROGUE_CR_CLK_STATUS_TE_SHIFT 2U |
| #define ROGUE_CR_CLK_STATUS_TE_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_CLK_STATUS_TE_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_TE_RUNNING 0x0000000000000004ULL |
| #define ROGUE_CR_CLK_STATUS_TSP_SHIFT 1U |
| #define ROGUE_CR_CLK_STATUS_TSP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_CLK_STATUS_TSP_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_TSP_RUNNING 0x0000000000000002ULL |
| #define ROGUE_CR_CLK_STATUS_ISP_SHIFT 0U |
| #define ROGUE_CR_CLK_STATUS_ISP_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_CLK_STATUS_ISP_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS_ISP_RUNNING 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_CORE_ID */ |
| #define ROGUE_CR_CORE_ID__PBVNC 0x0020U |
| #define ROGUE_CR_CORE_ID__PBVNC__MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_SHIFT 48U |
| #define ROGUE_CR_CORE_ID__PBVNC__BRANCH_ID_CLRMSK 0x0000FFFFFFFFFFFFULL |
| #define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_SHIFT 32U |
| #define ROGUE_CR_CORE_ID__PBVNC__VERSION_ID_CLRMSK 0xFFFF0000FFFFFFFFULL |
| #define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_SHIFT 16U |
| #define ROGUE_CR_CORE_ID__PBVNC__NUMBER_OF_SCALABLE_UNITS_CLRMSK 0xFFFFFFFF0000FFFFULL |
| #define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_SHIFT 0U |
| #define ROGUE_CR_CORE_ID__PBVNC__CONFIG_ID_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_CORE_ID */ |
| #define ROGUE_CR_CORE_ID 0x0018U |
| #define ROGUE_CR_CORE_ID_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_CORE_ID_ID_SHIFT 16U |
| #define ROGUE_CR_CORE_ID_ID_CLRMSK 0x0000FFFFU |
| #define ROGUE_CR_CORE_ID_CONFIG_SHIFT 0U |
| #define ROGUE_CR_CORE_ID_CONFIG_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_CORE_REVISION */ |
| #define ROGUE_CR_CORE_REVISION 0x0020U |
| #define ROGUE_CR_CORE_REVISION_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_CORE_REVISION_DESIGNER_SHIFT 24U |
| #define ROGUE_CR_CORE_REVISION_DESIGNER_CLRMSK 0x00FFFFFFU |
| #define ROGUE_CR_CORE_REVISION_MAJOR_SHIFT 16U |
| #define ROGUE_CR_CORE_REVISION_MAJOR_CLRMSK 0xFF00FFFFU |
| #define ROGUE_CR_CORE_REVISION_MINOR_SHIFT 8U |
| #define ROGUE_CR_CORE_REVISION_MINOR_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_CORE_REVISION_MAINTENANCE_SHIFT 0U |
| #define ROGUE_CR_CORE_REVISION_MAINTENANCE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_DESIGNER_REV_FIELD1 */ |
| #define ROGUE_CR_DESIGNER_REV_FIELD1 0x0028U |
| #define ROGUE_CR_DESIGNER_REV_FIELD1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0U |
| #define ROGUE_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_DESIGNER_REV_FIELD2 */ |
| #define ROGUE_CR_DESIGNER_REV_FIELD2 0x0030U |
| #define ROGUE_CR_DESIGNER_REV_FIELD2_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0U |
| #define ROGUE_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_CHANGESET_NUMBER */ |
| #define ROGUE_CR_CHANGESET_NUMBER 0x0040U |
| #define ROGUE_CR_CHANGESET_NUMBER_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_SHIFT 0U |
| #define ROGUE_CR_CHANGESET_NUMBER_CHANGESET_NUMBER_CLRMSK 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_CLK_XTPLUS_CTRL */ |
| #define ROGUE_CR_CLK_XTPLUS_CTRL 0x0080U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_MASKFULL 0x0000003FFFFF0000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_SHIFT 36U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_CLRMSK 0xFFFFFFCFFFFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_ON 0x0000001000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_TDM_AUTO 0x0000002000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_SHIFT 34U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_CLRMSK 0xFFFFFFF3FFFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_ON 0x0000000400000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_ASTC_AUTO 0x0000000800000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_SHIFT 32U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_CLRMSK 0xFFFFFFFCFFFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_ON 0x0000000100000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_IPF_AUTO 0x0000000200000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_SHIFT 30U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_CLRMSK 0xFFFFFFFF3FFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_ON 0x0000000040000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_COMPUTE_AUTO 0x0000000080000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_SHIFT 28U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_CLRMSK 0xFFFFFFFFCFFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_ON 0x0000000010000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PIXEL_AUTO 0x0000000020000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_SHIFT 26U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_CLRMSK 0xFFFFFFFFF3FFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_ON 0x0000000004000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_VERTEX_AUTO 0x0000000008000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_SHIFT 24U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_CLRMSK 0xFFFFFFFFFCFFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_ON 0x0000000001000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USCPS_AUTO 0x0000000002000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_SHIFT 22U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_CLRMSK 0xFFFFFFFFFF3FFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_ON 0x0000000000400000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_PDS_SHARED_AUTO 0x0000000000800000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_SHIFT 20U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFCFFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_ON 0x0000000000100000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_BIF_BLACKPEARL_AUTO 0x0000000000200000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_SHIFT 18U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_CLRMSK 0xFFFFFFFFFFF3FFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_ON 0x0000000000040000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_USC_SHARED_AUTO 0x0000000000080000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_SHIFT 16U |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_CLRMSK 0xFFFFFFFFFFFCFFFFULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_ON 0x0000000000010000ULL |
| #define ROGUE_CR_CLK_XTPLUS_CTRL_GEOMETRY_AUTO 0x0000000000020000ULL |
| |
| /* Register ROGUE_CR_CLK_XTPLUS_STATUS */ |
| #define ROGUE_CR_CLK_XTPLUS_STATUS 0x0088U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_MASKFULL 0x00000000000007FFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_SHIFT 10U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_TDM_RUNNING 0x0000000000000400ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_SHIFT 9U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_CLRMSK 0xFFFFFFFFFFFFFDFFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_IPF_RUNNING 0x0000000000000200ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_SHIFT 8U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_COMPUTE_RUNNING 0x0000000000000100ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_SHIFT 7U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_CLRMSK 0xFFFFFFFFFFFFFF7FULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_ASTC_RUNNING 0x0000000000000080ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_SHIFT 6U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFBFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PIXEL_RUNNING 0x0000000000000040ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_SHIFT 5U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_VERTEX_RUNNING 0x0000000000000020ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_SHIFT 4U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USCPS_RUNNING 0x0000000000000010ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_SHIFT 3U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_PDS_SHARED_RUNNING 0x0000000000000008ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_SHIFT 2U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_BIF_BLACKPEARL_RUNNING 0x0000000000000004ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_SHIFT 1U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_USC_SHARED_RUNNING 0x0000000000000002ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_SHIFT 0U |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_XTPLUS_STATUS_GEOMETRY_RUNNING 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_SOFT_RESET */ |
| #define ROGUE_CR_SOFT_RESET 0x0100U |
| #define ROGUE_CR_SOFT_RESET__PBE2_XE__MASKFULL 0xFFEFFFFFFFFFFC3DULL |
| #define ROGUE_CR_SOFT_RESET_MASKFULL 0x00E7FFFFFFFFFC3DULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_SHIFT 63U |
| #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_CLRMSK 0x7FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM3_CORE_EN 0x8000000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_SHIFT 62U |
| #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM2_CORE_EN 0x4000000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_SHIFT 61U |
| #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO2_CORE_EN 0x2000000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_JONES_CORE_SHIFT 60U |
| #define ROGUE_CR_SOFT_RESET_JONES_CORE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_JONES_CORE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_TILING_CORE_SHIFT 59U |
| #define ROGUE_CR_SOFT_RESET_TILING_CORE_CLRMSK 0xF7FFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_TILING_CORE_EN 0x0800000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_TE3_SHIFT 58U |
| #define ROGUE_CR_SOFT_RESET_TE3_CLRMSK 0xFBFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_TE3_EN 0x0400000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_VCE_SHIFT 57U |
| #define ROGUE_CR_SOFT_RESET_VCE_CLRMSK 0xFDFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_VCE_EN 0x0200000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_VBS_SHIFT 56U |
| #define ROGUE_CR_SOFT_RESET_VBS_CLRMSK 0xFEFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_VBS_EN 0x0100000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DPX1_CORE_SHIFT 55U |
| #define ROGUE_CR_SOFT_RESET_DPX1_CORE_CLRMSK 0xFF7FFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DPX1_CORE_EN 0x0080000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DPX0_CORE_SHIFT 54U |
| #define ROGUE_CR_SOFT_RESET_DPX0_CORE_CLRMSK 0xFFBFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DPX0_CORE_EN 0x0040000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_FBA_SHIFT 53U |
| #define ROGUE_CR_SOFT_RESET_FBA_CLRMSK 0xFFDFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_FBA_EN 0x0020000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_FB_CDC_SHIFT 51U |
| #define ROGUE_CR_SOFT_RESET_FB_CDC_CLRMSK 0xFFF7FFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_FB_CDC_EN 0x0008000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_SH_SHIFT 50U |
| #define ROGUE_CR_SOFT_RESET_SH_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_SH_EN 0x0004000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_VRDM_SHIFT 49U |
| #define ROGUE_CR_SOFT_RESET_VRDM_CLRMSK 0xFFFDFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_VRDM_EN 0x0002000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_MCU_FBTC_SHIFT 48U |
| #define ROGUE_CR_SOFT_RESET_MCU_FBTC_CLRMSK 0xFFFEFFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_MCU_FBTC_EN 0x0001000000000000ULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_SHIFT 47U |
| #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_CLRMSK 0xFFFF7FFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM1_CORE_EN 0x0000800000000000ULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_SHIFT 46U |
| #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_CLRMSK 0xFFFFBFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_PHANTOM0_CORE_EN 0x0000400000000000ULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_SHIFT 45U |
| #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_CLRMSK 0xFFFFDFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO1_CORE_EN 0x0000200000000000ULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_SHIFT 44U |
| #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_CLRMSK 0xFFFFEFFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BERNADO0_CORE_EN 0x0000100000000000ULL |
| #define ROGUE_CR_SOFT_RESET_IPP_SHIFT 43U |
| #define ROGUE_CR_SOFT_RESET_IPP_CLRMSK 0xFFFFF7FFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_IPP_EN 0x0000080000000000ULL |
| #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_SHIFT 42U |
| #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_CLRMSK 0xFFFFFBFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BIF_TEXAS_EN 0x0000040000000000ULL |
| #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_SHIFT 41U |
| #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_CLRMSK 0xFFFFFDFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_TORNADO_CORE_EN 0x0000020000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_SHIFT 40U |
| #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_CLRMSK 0xFFFFFEFFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_H_CORE_EN 0x0000010000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_SHIFT 39U |
| #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_CLRMSK 0xFFFFFF7FFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_G_CORE_EN 0x0000008000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_SHIFT 38U |
| #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_CLRMSK 0xFFFFFFBFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_F_CORE_EN 0x0000004000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_SHIFT 37U |
| #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_CLRMSK 0xFFFFFFDFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_E_CORE_EN 0x0000002000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_SHIFT 36U |
| #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_CLRMSK 0xFFFFFFEFFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_D_CORE_EN 0x0000001000000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_SHIFT 35U |
| #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_CLRMSK 0xFFFFFFF7FFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_C_CORE_EN 0x0000000800000000ULL |
| #define ROGUE_CR_SOFT_RESET_MMU_SHIFT 34U |
| #define ROGUE_CR_SOFT_RESET_MMU_CLRMSK 0xFFFFFFFBFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_MMU_EN 0x0000000400000000ULL |
| #define ROGUE_CR_SOFT_RESET_BIF1_SHIFT 33U |
| #define ROGUE_CR_SOFT_RESET_BIF1_CLRMSK 0xFFFFFFFDFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BIF1_EN 0x0000000200000000ULL |
| #define ROGUE_CR_SOFT_RESET_GARTEN_SHIFT 32U |
| #define ROGUE_CR_SOFT_RESET_GARTEN_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_GARTEN_EN 0x0000000100000000ULL |
| #define ROGUE_CR_SOFT_RESET_CPU_SHIFT 32U |
| #define ROGUE_CR_SOFT_RESET_CPU_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_CPU_EN 0x0000000100000000ULL |
| #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_SHIFT 31U |
| #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_RASCAL_CORE_EN 0x0000000080000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_SHIFT 30U |
| #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_CLRMSK 0xFFFFFFFFBFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_B_CORE_EN 0x0000000040000000ULL |
| #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_SHIFT 29U |
| #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_CLRMSK 0xFFFFFFFFDFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_DUST_A_CORE_EN 0x0000000020000000ULL |
| #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_SHIFT 28U |
| #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_CLRMSK 0xFFFFFFFFEFFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_FB_TLCACHE_EN 0x0000000010000000ULL |
| #define ROGUE_CR_SOFT_RESET_SLC_SHIFT 27U |
| #define ROGUE_CR_SOFT_RESET_SLC_CLRMSK 0xFFFFFFFFF7FFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_SLC_EN 0x0000000008000000ULL |
| #define ROGUE_CR_SOFT_RESET_TLA_SHIFT 26U |
| #define ROGUE_CR_SOFT_RESET_TLA_CLRMSK 0xFFFFFFFFFBFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_TLA_EN 0x0000000004000000ULL |
| #define ROGUE_CR_SOFT_RESET_UVS_SHIFT 25U |
| #define ROGUE_CR_SOFT_RESET_UVS_CLRMSK 0xFFFFFFFFFDFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_UVS_EN 0x0000000002000000ULL |
| #define ROGUE_CR_SOFT_RESET_TE_SHIFT 24U |
| #define ROGUE_CR_SOFT_RESET_TE_CLRMSK 0xFFFFFFFFFEFFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_TE_EN 0x0000000001000000ULL |
| #define ROGUE_CR_SOFT_RESET_GPP_SHIFT 23U |
| #define ROGUE_CR_SOFT_RESET_GPP_CLRMSK 0xFFFFFFFFFF7FFFFFULL |
| #define ROGUE_CR_SOFT_RESET_GPP_EN 0x0000000000800000ULL |
| #define ROGUE_CR_SOFT_RESET_FBDC_SHIFT 22U |
| #define ROGUE_CR_SOFT_RESET_FBDC_CLRMSK 0xFFFFFFFFFFBFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_FBDC_EN 0x0000000000400000ULL |
| #define ROGUE_CR_SOFT_RESET_FBC_SHIFT 21U |
| #define ROGUE_CR_SOFT_RESET_FBC_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_FBC_EN 0x0000000000200000ULL |
| #define ROGUE_CR_SOFT_RESET_PM_SHIFT 20U |
| #define ROGUE_CR_SOFT_RESET_PM_CLRMSK 0xFFFFFFFFFFEFFFFFULL |
| #define ROGUE_CR_SOFT_RESET_PM_EN 0x0000000000100000ULL |
| #define ROGUE_CR_SOFT_RESET_PBE_SHIFT 19U |
| #define ROGUE_CR_SOFT_RESET_PBE_CLRMSK 0xFFFFFFFFFFF7FFFFULL |
| #define ROGUE_CR_SOFT_RESET_PBE_EN 0x0000000000080000ULL |
| #define ROGUE_CR_SOFT_RESET_USC_SHARED_SHIFT 18U |
| #define ROGUE_CR_SOFT_RESET_USC_SHARED_CLRMSK 0xFFFFFFFFFFFBFFFFULL |
| #define ROGUE_CR_SOFT_RESET_USC_SHARED_EN 0x0000000000040000ULL |
| #define ROGUE_CR_SOFT_RESET_MCU_L1_SHIFT 17U |
| #define ROGUE_CR_SOFT_RESET_MCU_L1_CLRMSK 0xFFFFFFFFFFFDFFFFULL |
| #define ROGUE_CR_SOFT_RESET_MCU_L1_EN 0x0000000000020000ULL |
| #define ROGUE_CR_SOFT_RESET_BIF_SHIFT 16U |
| #define ROGUE_CR_SOFT_RESET_BIF_CLRMSK 0xFFFFFFFFFFFEFFFFULL |
| #define ROGUE_CR_SOFT_RESET_BIF_EN 0x0000000000010000ULL |
| #define ROGUE_CR_SOFT_RESET_CDM_SHIFT 15U |
| #define ROGUE_CR_SOFT_RESET_CDM_CLRMSK 0xFFFFFFFFFFFF7FFFULL |
| #define ROGUE_CR_SOFT_RESET_CDM_EN 0x0000000000008000ULL |
| #define ROGUE_CR_SOFT_RESET_VDM_SHIFT 14U |
| #define ROGUE_CR_SOFT_RESET_VDM_CLRMSK 0xFFFFFFFFFFFFBFFFULL |
| #define ROGUE_CR_SOFT_RESET_VDM_EN 0x0000000000004000ULL |
| #define ROGUE_CR_SOFT_RESET_TESS_SHIFT 13U |
| #define ROGUE_CR_SOFT_RESET_TESS_CLRMSK 0xFFFFFFFFFFFFDFFFULL |
| #define ROGUE_CR_SOFT_RESET_TESS_EN 0x0000000000002000ULL |
| #define ROGUE_CR_SOFT_RESET_PDS_SHIFT 12U |
| #define ROGUE_CR_SOFT_RESET_PDS_CLRMSK 0xFFFFFFFFFFFFEFFFULL |
| #define ROGUE_CR_SOFT_RESET_PDS_EN 0x0000000000001000ULL |
| #define ROGUE_CR_SOFT_RESET_ISP_SHIFT 11U |
| #define ROGUE_CR_SOFT_RESET_ISP_CLRMSK 0xFFFFFFFFFFFFF7FFULL |
| #define ROGUE_CR_SOFT_RESET_ISP_EN 0x0000000000000800ULL |
| #define ROGUE_CR_SOFT_RESET_TSP_SHIFT 10U |
| #define ROGUE_CR_SOFT_RESET_TSP_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_SOFT_RESET_TSP_EN 0x0000000000000400ULL |
| #define ROGUE_CR_SOFT_RESET_SYSARB_SHIFT 5U |
| #define ROGUE_CR_SOFT_RESET_SYSARB_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_SOFT_RESET_SYSARB_EN 0x0000000000000020ULL |
| #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_SHIFT 4U |
| #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_SOFT_RESET_TPU_MCU_DEMUX_EN 0x0000000000000010ULL |
| #define ROGUE_CR_SOFT_RESET_MCU_L0_SHIFT 3U |
| #define ROGUE_CR_SOFT_RESET_MCU_L0_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_SOFT_RESET_MCU_L0_EN 0x0000000000000008ULL |
| #define ROGUE_CR_SOFT_RESET_TPU_SHIFT 2U |
| #define ROGUE_CR_SOFT_RESET_TPU_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_SOFT_RESET_TPU_EN 0x0000000000000004ULL |
| #define ROGUE_CR_SOFT_RESET_USC_SHIFT 0U |
| #define ROGUE_CR_SOFT_RESET_USC_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_SOFT_RESET_USC_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_SOFT_RESET2 */ |
| #define ROGUE_CR_SOFT_RESET2 0x0108U |
| #define ROGUE_CR_SOFT_RESET2_MASKFULL 0x00000000001FFFFFULL |
| #define ROGUE_CR_SOFT_RESET2_SPFILTER_SHIFT 12U |
| #define ROGUE_CR_SOFT_RESET2_SPFILTER_CLRMSK 0xFFE00FFFU |
| #define ROGUE_CR_SOFT_RESET2_TDM_SHIFT 11U |
| #define ROGUE_CR_SOFT_RESET2_TDM_CLRMSK 0xFFFFF7FFU |
| #define ROGUE_CR_SOFT_RESET2_TDM_EN 0x00000800U |
| #define ROGUE_CR_SOFT_RESET2_ASTC_SHIFT 10U |
| #define ROGUE_CR_SOFT_RESET2_ASTC_CLRMSK 0xFFFFFBFFU |
| #define ROGUE_CR_SOFT_RESET2_ASTC_EN 0x00000400U |
| #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_SHIFT 9U |
| #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_SOFT_RESET2_BLACKPEARL_EN 0x00000200U |
| #define ROGUE_CR_SOFT_RESET2_USCPS_SHIFT 8U |
| #define ROGUE_CR_SOFT_RESET2_USCPS_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_SOFT_RESET2_USCPS_EN 0x00000100U |
| #define ROGUE_CR_SOFT_RESET2_IPF_SHIFT 7U |
| #define ROGUE_CR_SOFT_RESET2_IPF_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_SOFT_RESET2_IPF_EN 0x00000080U |
| #define ROGUE_CR_SOFT_RESET2_GEOMETRY_SHIFT 6U |
| #define ROGUE_CR_SOFT_RESET2_GEOMETRY_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SOFT_RESET2_GEOMETRY_EN 0x00000040U |
| #define ROGUE_CR_SOFT_RESET2_USC_SHARED_SHIFT 5U |
| #define ROGUE_CR_SOFT_RESET2_USC_SHARED_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SOFT_RESET2_USC_SHARED_EN 0x00000020U |
| #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_SHIFT 4U |
| #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SOFT_RESET2_PDS_SHARED_EN 0x00000010U |
| #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_SHIFT 3U |
| #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SOFT_RESET2_BIF_BLACKPEARL_EN 0x00000008U |
| #define ROGUE_CR_SOFT_RESET2_PIXEL_SHIFT 2U |
| #define ROGUE_CR_SOFT_RESET2_PIXEL_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SOFT_RESET2_PIXEL_EN 0x00000004U |
| #define ROGUE_CR_SOFT_RESET2_CDM_SHIFT 1U |
| #define ROGUE_CR_SOFT_RESET2_CDM_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SOFT_RESET2_CDM_EN 0x00000002U |
| #define ROGUE_CR_SOFT_RESET2_VERTEX_SHIFT 0U |
| #define ROGUE_CR_SOFT_RESET2_VERTEX_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SOFT_RESET2_VERTEX_EN 0x00000001U |
| |
| /* Register ROGUE_CR_EVENT_STATUS */ |
| #define ROGUE_CR_EVENT_STATUS 0x0130U |
| #define ROGUE_CR_EVENT_STATUS__ROGUEXE__MASKFULL 0x00000000E01DFFFFULL |
| #define ROGUE_CR_EVENT_STATUS__SIGNALS__MASKFULL 0x00000000E007FFFFULL |
| #define ROGUE_CR_EVENT_STATUS_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_SHIFT 31U |
| #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_CLRMSK 0x7FFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_TDM_FENCE_FINISHED_EN 0x80000000U |
| #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_SHIFT 30U |
| #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_TDM_BUFFER_STALL_EN 0x40000000U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_SHIFT 29U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_SIGNAL_FAILURE_EN 0x20000000U |
| #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_SHIFT 28U |
| #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_DPX_OUT_OF_MEMORY_EN 0x10000000U |
| #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_SHIFT 27U |
| #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_CLRMSK 0xF7FFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_DPX_MMU_PAGE_FAULT_EN 0x08000000U |
| #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_SHIFT 26U |
| #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_CLRMSK 0xFBFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_RPM_OUT_OF_MEMORY_EN 0x04000000U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_SHIFT 25U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_CLRMSK 0xFDFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC3_FINISHED_EN 0x02000000U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_SHIFT 24U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_CLRMSK 0xFEFFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC2_FINISHED_EN 0x01000000U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_SHIFT 23U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_CLRMSK 0xFF7FFFFFU |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC1_FINISHED_EN 0x00800000U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_SHIFT 22U |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_CLRMSK 0xFFBFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_FBA_FC0_FINISHED_EN 0x00400000U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_SHIFT 21U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_CLRMSK 0xFFDFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC3_FINISHED_EN 0x00200000U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_SHIFT 20U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC2_FINISHED_EN 0x00100000U |
| #define ROGUE_CR_EVENT_STATUS_SAFETY_SHIFT 20U |
| #define ROGUE_CR_EVENT_STATUS_SAFETY_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_EVENT_STATUS_SAFETY_EN 0x00100000U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_SHIFT 19U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_CLRMSK 0xFFF7FFFFU |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC1_FINISHED_EN 0x00080000U |
| #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_SHIFT 19U |
| #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_CLRMSK 0xFFF7FFFFU |
| #define ROGUE_CR_EVENT_STATUS_SLAVE_REQ_EN 0x00080000U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_SHIFT 18U |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_CLRMSK 0xFFFBFFFFU |
| #define ROGUE_CR_EVENT_STATUS_RDM_FC0_FINISHED_EN 0x00040000U |
| #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_SHIFT 18U |
| #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_CLRMSK 0xFFFBFFFFU |
| #define ROGUE_CR_EVENT_STATUS_TDM_CONTEXT_STORE_FINISHED_EN 0x00040000U |
| #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_SHIFT 17U |
| #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_CLRMSK 0xFFFDFFFFU |
| #define ROGUE_CR_EVENT_STATUS_SHG_FINISHED_EN 0x00020000U |
| #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_SHIFT 17U |
| #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_CLRMSK 0xFFFDFFFFU |
| #define ROGUE_CR_EVENT_STATUS_SPFILTER_SIGNAL_UPDATE_EN 0x00020000U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_SHIFT 16U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_CLRMSK 0xFFFEFFFFU |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_BUFFER_STALL_EN 0x00010000U |
| #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_SHIFT 15U |
| #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_CLRMSK 0xFFFF7FFFU |
| #define ROGUE_CR_EVENT_STATUS_USC_TRIGGER_EN 0x00008000U |
| #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_SHIFT 14U |
| #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_CLRMSK 0xFFFFBFFFU |
| #define ROGUE_CR_EVENT_STATUS_ZLS_FINISHED_EN 0x00004000U |
| #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_SHIFT 13U |
| #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_CLRMSK 0xFFFFDFFFU |
| #define ROGUE_CR_EVENT_STATUS_GPIO_ACK_EN 0x00002000U |
| #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_SHIFT 12U |
| #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_CLRMSK 0xFFFFEFFFU |
| #define ROGUE_CR_EVENT_STATUS_GPIO_REQ_EN 0x00001000U |
| #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_SHIFT 11U |
| #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_CLRMSK 0xFFFFF7FFU |
| #define ROGUE_CR_EVENT_STATUS_POWER_ABORT_EN 0x00000800U |
| #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_SHIFT 10U |
| #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_CLRMSK 0xFFFFFBFFU |
| #define ROGUE_CR_EVENT_STATUS_POWER_COMPLETE_EN 0x00000400U |
| #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_SHIFT 9U |
| #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_EVENT_STATUS_MMU_PAGE_FAULT_EN 0x00000200U |
| #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_SHIFT 8U |
| #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_EVENT_STATUS_PM_3D_MEM_FREE_EN 0x00000100U |
| #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_SHIFT 7U |
| #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_EVENT_STATUS_PM_OUT_OF_MEMORY_EN 0x00000080U |
| #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 6U |
| #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_EVENT_STATUS_TA_TERMINATE_EN 0x00000040U |
| #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_SHIFT 5U |
| #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_EVENT_STATUS_TA_FINISHED_EN 0x00000020U |
| #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_SHIFT 4U |
| #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_EVENT_STATUS_ISP_END_MACROTILE_EN 0x00000010U |
| #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 3U |
| #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_EVENT_STATUS_PIXELBE_END_RENDER_EN 0x00000008U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_SHIFT 2U |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_EVENT_STATUS_COMPUTE_FINISHED_EN 0x00000004U |
| #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_SHIFT 1U |
| #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_EVENT_STATUS_KERNEL_FINISHED_EN 0x00000002U |
| #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_SHIFT 0U |
| #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_EVENT_STATUS_TLA_COMPLETE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TIMER */ |
| #define ROGUE_CR_TIMER 0x0160U |
| #define ROGUE_CR_TIMER_MASKFULL 0x8000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TIMER_BIT31_SHIFT 63U |
| #define ROGUE_CR_TIMER_BIT31_CLRMSK 0x7FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_TIMER_BIT31_EN 0x8000000000000000ULL |
| #define ROGUE_CR_TIMER_VALUE_SHIFT 0U |
| #define ROGUE_CR_TIMER_VALUE_CLRMSK 0xFFFF000000000000ULL |
| |
| /* Register ROGUE_CR_TLA_STATUS */ |
| #define ROGUE_CR_TLA_STATUS 0x0178U |
| #define ROGUE_CR_TLA_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_TLA_STATUS_BLIT_COUNT_SHIFT 39U |
| #define ROGUE_CR_TLA_STATUS_BLIT_COUNT_CLRMSK 0x0000007FFFFFFFFFULL |
| #define ROGUE_CR_TLA_STATUS_REQUEST_SHIFT 7U |
| #define ROGUE_CR_TLA_STATUS_REQUEST_CLRMSK 0xFFFFFF800000007FULL |
| #define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_SHIFT 1U |
| #define ROGUE_CR_TLA_STATUS_FIFO_FULLNESS_CLRMSK 0xFFFFFFFFFFFFFF81ULL |
| #define ROGUE_CR_TLA_STATUS_BUSY_SHIFT 0U |
| #define ROGUE_CR_TLA_STATUS_BUSY_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_TLA_STATUS_BUSY_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_PM_PARTIAL_RENDER_ENABLE */ |
| #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE 0x0338U |
| #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_SHIFT 0U |
| #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_PM_PARTIAL_RENDER_ENABLE_OP_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SIDEKICK_IDLE */ |
| #define ROGUE_CR_SIDEKICK_IDLE 0x03C8U |
| #define ROGUE_CR_SIDEKICK_IDLE_MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_SHIFT 6U |
| #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SIDEKICK_IDLE_FB_CDC_EN 0x00000040U |
| #define ROGUE_CR_SIDEKICK_IDLE_MMU_SHIFT 5U |
| #define ROGUE_CR_SIDEKICK_IDLE_MMU_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SIDEKICK_IDLE_MMU_EN 0x00000020U |
| #define ROGUE_CR_SIDEKICK_IDLE_BIF128_SHIFT 4U |
| #define ROGUE_CR_SIDEKICK_IDLE_BIF128_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SIDEKICK_IDLE_BIF128_EN 0x00000010U |
| #define ROGUE_CR_SIDEKICK_IDLE_TLA_SHIFT 3U |
| #define ROGUE_CR_SIDEKICK_IDLE_TLA_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SIDEKICK_IDLE_TLA_EN 0x00000008U |
| #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_SHIFT 2U |
| #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SIDEKICK_IDLE_GARTEN_EN 0x00000004U |
| #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_SHIFT 1U |
| #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SIDEKICK_IDLE_HOSTIF_EN 0x00000002U |
| #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_SHIFT 0U |
| #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SIDEKICK_IDLE_SOCIF_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MARS_IDLE */ |
| #define ROGUE_CR_MARS_IDLE 0x08F8U |
| #define ROGUE_CR_MARS_IDLE_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_SHIFT 2U |
| #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_MARS_IDLE_MH_SYSARB0_EN 0x00000004U |
| #define ROGUE_CR_MARS_IDLE_CPU_SHIFT 1U |
| #define ROGUE_CR_MARS_IDLE_CPU_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_MARS_IDLE_CPU_EN 0x00000002U |
| #define ROGUE_CR_MARS_IDLE_SOCIF_SHIFT 0U |
| #define ROGUE_CR_MARS_IDLE_SOCIF_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MARS_IDLE_SOCIF_EN 0x00000001U |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_STORE_STATUS */ |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS 0x0430U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_MASKFULL 0x00000000000000F3ULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_SHIFT 4U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_LAST_PIPE_CLRMSK 0xFFFFFF0FU |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_VDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK0 */ |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0 0x0438U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_SHIFT 32U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK1 */ |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1 0x0440U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK1_PDS_STATE2_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_STORE_TASK2 */ |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2 0x0448U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_SHIFT 32U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 */ |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0 0x0450U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_SHIFT 32U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE1_CLRMSK 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK0_PDS_STATE0_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 */ |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1 0x0458U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK1_PDS_STATE2_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 */ |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2 0x0460U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_SHIFT 32U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT2_CLRMSK 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_RESUME_TASK2_STREAM_OUT1_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_CDM_CONTEXT_STORE_STATUS */ |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS 0x04A0U |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_SHIFT 1U |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_NEED_RESUME_EN 0x00000002U |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_SHIFT 0U |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_CDM_CONTEXT_STORE_STATUS_COMPLETE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_CDM_CONTEXT_PDS0 */ |
| #define ROGUE_CR_CDM_CONTEXT_PDS0 0x04A8U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_SHIFT 36U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_DATA_ADDR_ALIGNSIZE 16U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_SHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_PDS0_CODE_ADDR_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_CDM_CONTEXT_PDS1 */ |
| #define ROGUE_CR_CDM_CONTEXT_PDS1 0x04B0U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_MASKFULL 0x000000003FFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_PDS_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_SHIFT 28U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_USC_SEQ_DEP_EN 0x10000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_SHIFT 28U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_SHIFT 27U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_CLRMSK 0xF7FFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_TARGET_EN 0x08000000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_SHIFT 21U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_SHIFT 20U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SHARED_EN 0x00100000U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_SHIFT 11U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_SHIFT 1U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_SHIFT 0U |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_CDM_CONTEXT_PDS1_FENCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_CDM_TERMINATE_PDS */ |
| #define ROGUE_CR_CDM_TERMINATE_PDS 0x04B8U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_MASKFULL 0xFFFFFFF0FFFFFFF0ULL |
| #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_SHIFT 36U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL |
| #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_DATA_ADDR_ALIGNSIZE 16U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_SHIFT 4U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL |
| #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_TERMINATE_PDS_CODE_ADDR_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_CDM_TERMINATE_PDS1 */ |
| #define ROGUE_CR_CDM_TERMINATE_PDS1 0x04C0U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_MASKFULL 0x000000003FFFFFFFULL |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_PDS_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_SHIFT 28U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_USC_SEQ_DEP_EN 0x10000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_SHIFT 28U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_SHIFT 27U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_CLRMSK 0xF7FFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_TARGET_EN 0x08000000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_SHIFT 21U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_SHIFT 20U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SHARED_EN 0x00100000U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_SHIFT 11U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_SHIFT 1U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_SHIFT 0U |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_CDM_TERMINATE_PDS1_FENCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 */ |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0 0x04D8U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_MASKFULL 0xFFFFFFF0FFFFFFF0ULL |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_SHIFT 36U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_CLRMSK 0x0000000FFFFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_DATA_ADDR_ALIGNSIZE 16U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_SHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_CLRMSK 0xFFFFFFFF0000000FULL |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS0_CODE_ADDR_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 */ |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1 0x04E0U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__MASKFULL 0x000000007FFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_MASKFULL 0x000000003FFFFFFFULL |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_SHIFT 30U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__PDS_SEQ_DEP_EN 0x40000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_PDS_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_SHIFT 29U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__USC_SEQ_DEP_EN 0x20000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_SHIFT 28U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_USC_SEQ_DEP_EN 0x10000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_SHIFT 28U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TARGET_EN 0x10000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_SHIFT 27U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_CLRMSK 0xF7FFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TARGET_EN 0x08000000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_SHIFT 22U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__UNIFIED_SIZE_CLRMSK 0xF03FFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_SHIFT 21U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_UNIFIED_SIZE_CLRMSK 0xF81FFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_SHIFT 21U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_CLRMSK 0xFFDFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SHARED_EN 0x00200000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_SHIFT 20U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SHARED_EN 0x00100000U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_SHIFT 12U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__COMMON_SIZE_CLRMSK 0xFFE00FFFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_SHIFT 11U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_COMMON_SIZE_CLRMSK 0xFFF007FFU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_TEMP_SIZE_CLRMSK 0xFFFFF87FU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_SHIFT 7U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1__TEMPSIZE8__TEMP_SIZE_CLRMSK 0xFFFFF07FU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_SHIFT 1U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_DATA_SIZE_CLRMSK 0xFFFFFF81U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_SHIFT 0U |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_CDM_CONTEXT_LOAD_PDS1_FENCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_CONFIG */ |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG 0x0810U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_MASKFULL 0x000001030F01FFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_SHIFT 40U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_CLRMSK 0xFFFFFEFFFFFFFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_FW_IDLE_ENABLE_EN 0x0000010000000000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_SHIFT 33U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_CLRMSK 0xFFFFFFFDFFFFFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_DISABLE_BOOT_EN 0x0000000200000000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_SHIFT 32U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_L2_CACHE_OFF_EN 0x0000000100000000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_SHIFT 25U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_OS_ID_CLRMSK 0xFFFFFFFFF1FFFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_SHIFT 24U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFEFFFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_TRUSTED_EN 0x0000000001000000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_SHIFT 16U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_CLRMSK 0xFFFFFFFFFFFEFFFFULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MIPS32 0x0000000000000000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_BOOT_ISA_MODE_MICROMIPS 0x0000000000010000ULL |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_CONFIG_REGBANK_BASE_ADDR_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1 0x0818U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MASKFULL 0x00000000FFFFF001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2 0x0820U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_SHIFT 6U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_TRUSTED_EN 0x0000000000000020ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP1_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1 0x0828U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MASKFULL 0x00000000FFFFF001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2 0x0830U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_SHIFT 6U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_TRUSTED_EN 0x0000000000000020ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP2_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1 0x0838U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MASKFULL 0x00000000FFFFF001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2 0x0840U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_SHIFT 6U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_TRUSTED_EN 0x0000000000000020ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP3_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1 0x0848U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MASKFULL 0x00000000FFFFF001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2 0x0850U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_SHIFT 6U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_TRUSTED_EN 0x0000000000000020ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP4_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1 0x0858U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MASKFULL 0x00000000FFFFF001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG1_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2 0x0860U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_MASKFULL 0x000000FFFFFFF1FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_ADDR_OUT_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_SHIFT 6U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_OS_ID_CLRMSK 0xFFFFFFFFFFFFFE3FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_TRUSTED_EN 0x0000000000000020ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP5_CONFIG2_REGION_SIZE_POW2_CLRMSK 0xFFFFFFFFFFFFFFE0ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS 0x0868U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_MASKFULL 0x00000001FFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_SHIFT 32U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_EVENT_EN 0x0000000100000000ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_ADDRESS_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR 0x0870U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_EVENT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG 0x0878U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MASKFULL 0xFFFFFFF7FFFFFFBFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_SHIFT 36U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_SHIFT 32U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_SHIFT 11U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_TRUSTED_EN 0x0000000000000800ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_SHIFT 7U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4KB 0x0000000000000000ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16KB 0x0000000000000080ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64KB 0x0000000000000100ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256KB 0x0000000000000180ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_1MB 0x0000000000000200ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_4MB 0x0000000000000280ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_16MB 0x0000000000000300ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_64MB 0x0000000000000380ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_REGION_SIZE_256MB 0x0000000000000400ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_SHIFT 1U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_ENTRY_CLRMSK 0xFFFFFFFFFFFFFFC1ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ 0x0880U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_MASKFULL 0x000000000000003FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_SHIFT 1U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_ENTRY_CLRMSK 0xFFFFFFC1U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_READ_REQUEST_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA */ |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA 0x0888U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MASKFULL 0xFFFFFFF7FFFFFF81ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_SHIFT 36U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_ADDR_OUT_CLRMSK 0x0000000FFFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_SHIFT 32U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_OS_ID_CLRMSK 0xFFFFFFF8FFFFFFFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_SHIFT 12U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_BASE_ADDR_IN_CLRMSK 0xFFFFFFFF00000FFFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_SHIFT 11U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_CLRMSK 0xFFFFFFFFFFFFF7FFULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_TRUSTED_EN 0x0000000000000800ULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_SHIFT 7U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_REGION_SIZE_CLRMSK 0xFFFFFFFFFFFFF87FULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MIPS_ADDR_REMAP_RANGE_DATA_MODE_ENABLE_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE */ |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE 0x08A0U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_ENABLE_EVENT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS */ |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS 0x08A8U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR */ |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR 0x08B0U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE */ |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE 0x08B8U |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_ENABLE_EVENT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_NMI_EVENT */ |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT 0x08C0U |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_WRAPPER_NMI_EVENT_TRIGGER_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_DEBUG_CONFIG */ |
| #define ROGUE_CR_MIPS_DEBUG_CONFIG 0x08C8U |
| #define ROGUE_CR_MIPS_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_SHIFT 0U |
| #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_DEBUG_CONFIG_DISABLE_PROBE_DEBUG_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_EXCEPTION_STATUS */ |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS 0x08D0U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_MASKFULL 0x000000000000003FULL |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_SHIFT 5U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_SLEEP_EN 0x00000020U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_SHIFT 4U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NMI_TAKEN_EN 0x00000010U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_SHIFT 3U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_EXL_EN 0x00000008U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_SHIFT 2U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_NEST_ERL_EN 0x00000004U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_SHIFT 1U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_EXL_EN 0x00000002U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_SHIFT 0U |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MIPS_EXCEPTION_STATUS_SI_ERL_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MIPS_WRAPPER_STATUS */ |
| #define ROGUE_CR_MIPS_WRAPPER_STATUS 0x08E8U |
| #define ROGUE_CR_MIPS_WRAPPER_STATUS_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_SHIFT 0U |
| #define ROGUE_CR_MIPS_WRAPPER_STATUS_OUTSTANDING_REQUESTS_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_XPU_BROADCAST */ |
| #define ROGUE_CR_XPU_BROADCAST 0x0890U |
| #define ROGUE_CR_XPU_BROADCAST_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_XPU_BROADCAST_MASK_SHIFT 0U |
| #define ROGUE_CR_XPU_BROADCAST_MASK_CLRMSK 0xFFFFFE00U |
| |
| /* Register ROGUE_CR_META_SP_MSLVDATAX */ |
| #define ROGUE_CR_META_SP_MSLVDATAX 0x0A00U |
| #define ROGUE_CR_META_SP_MSLVDATAX_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVDATAX_MSLVDATAX_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVDATAT */ |
| #define ROGUE_CR_META_SP_MSLVDATAT 0x0A08U |
| #define ROGUE_CR_META_SP_MSLVDATAT_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVDATAT_MSLVDATAT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVCTRL0 */ |
| #define ROGUE_CR_META_SP_MSLVCTRL0 0x0A10U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_SHIFT 2U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_ADDR_CLRMSK 0x00000003U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_SHIFT 1U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_META_SP_MSLVCTRL0_AUTOINCR_EN 0x00000002U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_RD_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVCTRL0_RD_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_META_SP_MSLVCTRL0_RD_EN 0x00000001U |
| |
| /* Register ROGUE_CR_META_SP_MSLVCTRL1 */ |
| #define ROGUE_CR_META_SP_MSLVCTRL1 0x0A18U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_MASKFULL 0x00000000F7F4003FULL |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_SHIFT 30U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRTHREAD_CLRMSK 0x3FFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_SHIFT 29U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_LOCK2_INTERLOCK_EN 0x20000000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_SHIFT 28U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_ATOMIC_INTERLOCK_EN 0x10000000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_SHIFT 26U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_CLRMSK 0xFBFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN 0x04000000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_SHIFT 25U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_CLRMSK 0xFDFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_COREMEM_IDLE_EN 0x02000000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_READY_SHIFT 24U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_READY_CLRMSK 0xFEFFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_READY_EN 0x01000000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_SHIFT 21U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERRID_CLRMSK 0xFF1FFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_SHIFT 20U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_DEFERR_EN 0x00100000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_SHIFT 18U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_CLRMSK 0xFFFBFFFFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_WR_ACTIVE_EN 0x00040000U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_SHIFT 4U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_THREAD_CLRMSK 0xFFFFFFCFU |
| #define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_SHIFT 2U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_TRANS_SIZE_CLRMSK 0xFFFFFFF3U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVCTRL1_BYTE_ROUND_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_META_SP_MSLVHANDSHKE */ |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE 0x0A50U |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_SHIFT 2U |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE_INPUT_CLRMSK 0xFFFFFFF3U |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVHANDSHKE_OUTPUT_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_META_SP_MSLVT0KICK */ |
| #define ROGUE_CR_META_SP_MSLVT0KICK 0x0A80U |
| #define ROGUE_CR_META_SP_MSLVT0KICK_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT0KICK_MSLVT0KICK_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT0KICKI */ |
| #define ROGUE_CR_META_SP_MSLVT0KICKI 0x0A88U |
| #define ROGUE_CR_META_SP_MSLVT0KICKI_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT0KICKI_MSLVT0KICKI_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT1KICK */ |
| #define ROGUE_CR_META_SP_MSLVT1KICK 0x0A90U |
| #define ROGUE_CR_META_SP_MSLVT1KICK_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT1KICK_MSLVT1KICK_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT1KICKI */ |
| #define ROGUE_CR_META_SP_MSLVT1KICKI 0x0A98U |
| #define ROGUE_CR_META_SP_MSLVT1KICKI_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT1KICKI_MSLVT1KICKI_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT2KICK */ |
| #define ROGUE_CR_META_SP_MSLVT2KICK 0x0AA0U |
| #define ROGUE_CR_META_SP_MSLVT2KICK_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT2KICK_MSLVT2KICK_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT2KICKI */ |
| #define ROGUE_CR_META_SP_MSLVT2KICKI 0x0AA8U |
| #define ROGUE_CR_META_SP_MSLVT2KICKI_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT2KICKI_MSLVT2KICKI_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT3KICK */ |
| #define ROGUE_CR_META_SP_MSLVT3KICK 0x0AB0U |
| #define ROGUE_CR_META_SP_MSLVT3KICK_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT3KICK_MSLVT3KICK_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVT3KICKI */ |
| #define ROGUE_CR_META_SP_MSLVT3KICKI 0x0AB8U |
| #define ROGUE_CR_META_SP_MSLVT3KICKI_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVT3KICKI_MSLVT3KICKI_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_META_SP_MSLVRST */ |
| #define ROGUE_CR_META_SP_MSLVRST 0x0AC0U |
| #define ROGUE_CR_META_SP_MSLVRST_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_META_SP_MSLVRST_SOFTRESET_EN 0x00000001U |
| |
| /* Register ROGUE_CR_META_SP_MSLVIRQSTATUS */ |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS 0x0AC8U |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_MASKFULL 0x000000000000000CULL |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_SHIFT 3U |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT3_EN 0x00000008U |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_SHIFT 2U |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN 0x00000004U |
| |
| /* Register ROGUE_CR_META_SP_MSLVIRQENABLE */ |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE 0x0AD0U |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_MASKFULL 0x000000000000000CULL |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_SHIFT 3U |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT1_EN 0x00000008U |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_SHIFT 2U |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_META_SP_MSLVIRQENABLE_EVENT0_EN 0x00000004U |
| |
| /* Register ROGUE_CR_META_SP_MSLVIRQLEVEL */ |
| #define ROGUE_CR_META_SP_MSLVIRQLEVEL 0x0AD8U |
| #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_SHIFT 0U |
| #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_META_SP_MSLVIRQLEVEL_MODE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE */ |
| #define ROGUE_CR_MTS_SCHEDULE 0x0B00U |
| #define ROGUE_CR_MTS_SCHEDULE_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE1 */ |
| #define ROGUE_CR_MTS_SCHEDULE1 0x10B00U |
| #define ROGUE_CR_MTS_SCHEDULE1_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE1_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE1_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE1_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE1_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE1_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE1_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE1_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE1_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE1_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE1_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE1_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE2 */ |
| #define ROGUE_CR_MTS_SCHEDULE2 0x20B00U |
| #define ROGUE_CR_MTS_SCHEDULE2_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE2_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE2_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE2_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE2_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE2_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE2_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE2_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE2_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE2_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE2_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE2_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE3 */ |
| #define ROGUE_CR_MTS_SCHEDULE3 0x30B00U |
| #define ROGUE_CR_MTS_SCHEDULE3_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE3_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE3_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE3_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE3_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE3_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE3_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE3_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE3_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE3_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE3_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE3_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE4 */ |
| #define ROGUE_CR_MTS_SCHEDULE4 0x40B00U |
| #define ROGUE_CR_MTS_SCHEDULE4_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE4_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE4_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE4_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE4_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE4_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE4_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE4_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE4_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE4_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE4_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE4_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE5 */ |
| #define ROGUE_CR_MTS_SCHEDULE5 0x50B00U |
| #define ROGUE_CR_MTS_SCHEDULE5_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE5_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE5_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE5_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE5_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE5_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE5_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE5_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE5_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE5_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE5_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE5_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE6 */ |
| #define ROGUE_CR_MTS_SCHEDULE6 0x60B00U |
| #define ROGUE_CR_MTS_SCHEDULE6_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE6_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE6_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE6_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE6_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE6_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE6_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE6_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE6_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE6_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE6_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE6_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE7 */ |
| #define ROGUE_CR_MTS_SCHEDULE7 0x70B00U |
| #define ROGUE_CR_MTS_SCHEDULE7_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_MTS_SCHEDULE7_HOST_SHIFT 8U |
| #define ROGUE_CR_MTS_SCHEDULE7_HOST_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_MTS_SCHEDULE7_HOST_BG_TIMER 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE7_HOST_HOST 0x00000100U |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_SHIFT 6U |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT1 0x00000040U |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT2 0x00000080U |
| #define ROGUE_CR_MTS_SCHEDULE7_PRIORITY_PRT3 0x000000C0U |
| #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_SHIFT 5U |
| #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_BGCTX 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE7_CONTEXT_INTCTX 0x00000020U |
| #define ROGUE_CR_MTS_SCHEDULE7_TASK_SHIFT 4U |
| #define ROGUE_CR_MTS_SCHEDULE7_TASK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SCHEDULE7_TASK_NON_COUNTED 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE7_TASK_COUNTED 0x00000010U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_CLRMSK 0xFFFFFFF0U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM0 0x00000000U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM1 0x00000001U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM2 0x00000002U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM3 0x00000003U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM4 0x00000004U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM5 0x00000005U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM6 0x00000006U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM7 0x00000007U |
| #define ROGUE_CR_MTS_SCHEDULE7_DM_DM_ALL 0x0000000FU |
| |
| /* Register ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC */ |
| #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC 0x0B30U |
| #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U |
| #define ROGUE_CR_MTS_BGCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC */ |
| #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC 0x0B38U |
| #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U |
| #define ROGUE_CR_MTS_BGCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC */ |
| #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC 0x0B40U |
| #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_SHIFT 0U |
| #define ROGUE_CR_MTS_INTCTX_THREAD0_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC */ |
| #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC 0x0B48U |
| #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_SHIFT 0U |
| #define ROGUE_CR_MTS_INTCTX_THREAD1_DM_ASSOC_DM_ASSOC_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG */ |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG 0x0B50U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__MASKFULL 0x000FF0FFFFFFF701ULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_MASKFULL 0x0000FFFFFFFFF001ULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT 44U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK 0xFFFF0FFFFFFFFFFFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_SHIFT 44U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG__S7_TOP__FENCE_PC_BASE_CLRMSK 0xFFF00FFFFFFFFFFFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT 40U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_CLRMSK 0xFFFFF0FFFFFFFFFFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_SHIFT 12U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_SHIFT 9U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PERSISTENCE_CLRMSK 0xFFFFFFFFFFFFF9FFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_SHIFT 8U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_SLC_COHERENT_EN 0x0000000000000100ULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_SHIFT 0U |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META 0x0000000000000000ULL |
| #define ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_MTS 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE 0x0B58U |
| #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM0_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE 0x0B60U |
| #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM1_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE 0x0B68U |
| #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM2_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE 0x0B70U |
| #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM3_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE 0x0B78U |
| #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM4_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE */ |
| #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE 0x0B80U |
| #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MTS_DM5_INTERRUPT_ENABLE_INT_ENABLE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_INTCTX */ |
| #define ROGUE_CR_MTS_INTCTX 0x0B98U |
| #define ROGUE_CR_MTS_INTCTX_MASKFULL 0x000000003FFFFFFFULL |
| #define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_SHIFT 22U |
| #define ROGUE_CR_MTS_INTCTX_DM_HOST_SCHEDULE_CLRMSK 0xC03FFFFFU |
| #define ROGUE_CR_MTS_INTCTX_DM_PTR_SHIFT 18U |
| #define ROGUE_CR_MTS_INTCTX_DM_PTR_CLRMSK 0xFFC3FFFFU |
| #define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_SHIFT 16U |
| #define ROGUE_CR_MTS_INTCTX_THREAD_ACTIVE_CLRMSK 0xFFFCFFFFU |
| #define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_SHIFT 8U |
| #define ROGUE_CR_MTS_INTCTX_DM_TIMER_SCHEDULE_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_SHIFT 0U |
| #define ROGUE_CR_MTS_INTCTX_DM_INTERRUPT_SCHEDULE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_MTS_BGCTX */ |
| #define ROGUE_CR_MTS_BGCTX 0x0BA0U |
| #define ROGUE_CR_MTS_BGCTX_MASKFULL 0x0000000000003FFFULL |
| #define ROGUE_CR_MTS_BGCTX_DM_PTR_SHIFT 10U |
| #define ROGUE_CR_MTS_BGCTX_DM_PTR_CLRMSK 0xFFFFC3FFU |
| #define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_SHIFT 8U |
| #define ROGUE_CR_MTS_BGCTX_THREAD_ACTIVE_CLRMSK 0xFFFFFCFFU |
| #define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_SHIFT 0U |
| #define ROGUE_CR_MTS_BGCTX_DM_NONCOUNTED_SCHEDULE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE */ |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE 0x0BA8U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_SHIFT 56U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM7_CLRMSK 0x00FFFFFFFFFFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_SHIFT 48U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM6_CLRMSK 0xFF00FFFFFFFFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_SHIFT 40U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM5_CLRMSK 0xFFFF00FFFFFFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_SHIFT 32U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM4_CLRMSK 0xFFFFFF00FFFFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_SHIFT 24U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM3_CLRMSK 0xFFFFFFFF00FFFFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_SHIFT 16U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM2_CLRMSK 0xFFFFFFFFFF00FFFFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_SHIFT 8U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM1_CLRMSK 0xFFFFFFFFFFFF00FFULL |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_SHIFT 0U |
| #define ROGUE_CR_MTS_BGCTX_COUNTED_SCHEDULE_DM0_CLRMSK 0xFFFFFFFFFFFFFF00ULL |
| |
| /* Register ROGUE_CR_MTS_GPU_INT_STATUS */ |
| #define ROGUE_CR_MTS_GPU_INT_STATUS 0x0BB0U |
| #define ROGUE_CR_MTS_GPU_INT_STATUS_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_SHIFT 0U |
| #define ROGUE_CR_MTS_GPU_INT_STATUS_STATUS_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_MTS_SCHEDULE_ENABLE */ |
| #define ROGUE_CR_MTS_SCHEDULE_ENABLE 0x0BC8U |
| #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_SHIFT 0U |
| #define ROGUE_CR_MTS_SCHEDULE_ENABLE_MASK_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_IRQ_OS0_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS0_EVENT_STATUS 0x0BD8U |
| #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS0_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS0_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR 0x0BE8U |
| #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS0_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS1_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS1_EVENT_STATUS 0x10BD8U |
| #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS1_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS1_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR 0x10BE8U |
| #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS1_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS2_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS2_EVENT_STATUS 0x20BD8U |
| #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS2_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS2_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR 0x20BE8U |
| #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS2_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS3_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS3_EVENT_STATUS 0x30BD8U |
| #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS3_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS3_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR 0x30BE8U |
| #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS3_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS4_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS4_EVENT_STATUS 0x40BD8U |
| #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS4_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS4_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR 0x40BE8U |
| #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS4_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS5_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS5_EVENT_STATUS 0x50BD8U |
| #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS5_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS5_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR 0x50BE8U |
| #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS5_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS6_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS6_EVENT_STATUS 0x60BD8U |
| #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS6_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS6_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR 0x60BE8U |
| #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS6_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS7_EVENT_STATUS */ |
| #define ROGUE_CR_IRQ_OS7_EVENT_STATUS 0x70BD8U |
| #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS7_EVENT_STATUS_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_IRQ_OS7_EVENT_CLEAR */ |
| #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR 0x70BE8U |
| #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_SHIFT 0U |
| #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_IRQ_OS7_EVENT_CLEAR_SOURCE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_META_BOOT */ |
| #define ROGUE_CR_META_BOOT 0x0BF8U |
| #define ROGUE_CR_META_BOOT_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_META_BOOT_MODE_SHIFT 0U |
| #define ROGUE_CR_META_BOOT_MODE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_META_BOOT_MODE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_GARTEN_SLC */ |
| #define ROGUE_CR_GARTEN_SLC 0x0BB8U |
| #define ROGUE_CR_GARTEN_SLC_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_SHIFT 0U |
| #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_GARTEN_SLC_FORCE_COHERENCY_EN 0x00000001U |
| |
| /* Register ROGUE_CR_PPP */ |
| #define ROGUE_CR_PPP 0x0CD0U |
| #define ROGUE_CR_PPP_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PPP_CHECKSUM_SHIFT 0U |
| #define ROGUE_CR_PPP_CHECKSUM_CLRMSK 0x00000000U |
| |
| #define ROGUE_CR_ISP_RENDER_DIR_TYPE_MASK 0x00000003U |
| /* Top-left to bottom-right */ |
| #define ROGUE_CR_ISP_RENDER_DIR_TYPE_TL2BR 0x00000000U |
| /* Top-right to bottom-left */ |
| #define ROGUE_CR_ISP_RENDER_DIR_TYPE_TR2BL 0x00000001U |
| /* Bottom-left to top-right */ |
| #define ROGUE_CR_ISP_RENDER_DIR_TYPE_BL2TR 0x00000002U |
| /* Bottom-right to top-left */ |
| #define ROGUE_CR_ISP_RENDER_DIR_TYPE_BR2TL 0x00000003U |
| |
| #define ROGUE_CR_ISP_RENDER_MODE_TYPE_MASK 0x00000003U |
| /* Normal render */ |
| #define ROGUE_CR_ISP_RENDER_MODE_TYPE_NORM 0x00000000U |
| /* Fast 2D render */ |
| #define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_2D 0x00000002U |
| /* Fast scale render */ |
| #define ROGUE_CR_ISP_RENDER_MODE_TYPE_FAST_SCALE 0x00000003U |
| |
| /* Register ROGUE_CR_ISP_RENDER */ |
| #define ROGUE_CR_ISP_RENDER 0x0F08U |
| #define ROGUE_CR_ISP_RENDER_MASKFULL 0x00000000000001FFULL |
| #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_SHIFT 8U |
| #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_ISP_RENDER_FAST_RENDER_FORCE_PROTECT_EN 0x00000100U |
| #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_SHIFT 7U |
| #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_ISP_RENDER_PROCESS_PROTECTED_TILES_EN 0x00000080U |
| #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_SHIFT 6U |
| #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_ISP_RENDER_PROCESS_UNPROTECTED_TILES_EN 0x00000040U |
| #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_SHIFT 5U |
| #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_ISP_RENDER_DISABLE_EOMT_EN 0x00000020U |
| #define ROGUE_CR_ISP_RENDER_RESUME_SHIFT 4U |
| #define ROGUE_CR_ISP_RENDER_RESUME_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_ISP_RENDER_RESUME_EN 0x00000010U |
| #define ROGUE_CR_ISP_RENDER_DIR_SHIFT 2U |
| #define ROGUE_CR_ISP_RENDER_DIR_CLRMSK 0xFFFFFFF3U |
| #define ROGUE_CR_ISP_RENDER_DIR_TL2BR 0x00000000U |
| #define ROGUE_CR_ISP_RENDER_DIR_TR2BL 0x00000004U |
| #define ROGUE_CR_ISP_RENDER_DIR_BL2TR 0x00000008U |
| #define ROGUE_CR_ISP_RENDER_DIR_BR2TL 0x0000000CU |
| #define ROGUE_CR_ISP_RENDER_MODE_SHIFT 0U |
| #define ROGUE_CR_ISP_RENDER_MODE_CLRMSK 0xFFFFFFFCU |
| #define ROGUE_CR_ISP_RENDER_MODE_NORM 0x00000000U |
| #define ROGUE_CR_ISP_RENDER_MODE_FAST_2D 0x00000002U |
| #define ROGUE_CR_ISP_RENDER_MODE_FAST_SCALE 0x00000003U |
| |
| /* Register ROGUE_CR_ISP_CTL */ |
| #define ROGUE_CR_ISP_CTL 0x0F38U |
| #define ROGUE_CR_ISP_CTL_MASKFULL 0x00000000FFFFF3FFULL |
| #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_SHIFT 31U |
| #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_CLRMSK 0x7FFFFFFFU |
| #define ROGUE_CR_ISP_CTL_SKIP_INIT_HDRS_EN 0x80000000U |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_SHIFT 30U |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_EN 0x40000000U |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_SHIFT 29U |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_ISP_CTL_LINE_STYLE_PIX_EN 0x20000000U |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_SHIFT 28U |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_VERT_EN 0x10000000U |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_SHIFT 27U |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_CLRMSK 0xF7FFFFFFU |
| #define ROGUE_CR_ISP_CTL_PAIR_TILES_EN 0x08000000U |
| #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_SHIFT 26U |
| #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_CLRMSK 0xFBFFFFFFU |
| #define ROGUE_CR_ISP_CTL_CREQ_BUF_EN_EN 0x04000000U |
| #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_SHIFT 25U |
| #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_CLRMSK 0xFDFFFFFFU |
| #define ROGUE_CR_ISP_CTL_TILE_AGE_EN_EN 0x02000000U |
| #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_SHIFT 23U |
| #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_CLRMSK 0xFE7FFFFFU |
| #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX9 0x00000000U |
| #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_DX10 0x00800000U |
| #define ROGUE_CR_ISP_CTL_ISP_SAMPLE_POS_MODE_OGL 0x01000000U |
| #define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_SHIFT 21U |
| #define ROGUE_CR_ISP_CTL_NUM_TILES_PER_USC_CLRMSK 0xFF9FFFFFU |
| #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_SHIFT 20U |
| #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_ISP_CTL_DBIAS_IS_INT_EN 0x00100000U |
| #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_SHIFT 19U |
| #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_CLRMSK 0xFFF7FFFFU |
| #define ROGUE_CR_ISP_CTL_OVERLAP_CHECK_MODE_EN 0x00080000U |
| #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_SHIFT 18U |
| #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_CLRMSK 0xFFFBFFFFU |
| #define ROGUE_CR_ISP_CTL_PT_UPFRONT_DEPTH_DISABLE_EN 0x00040000U |
| #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_SHIFT 17U |
| #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_CLRMSK 0xFFFDFFFFU |
| #define ROGUE_CR_ISP_CTL_PROCESS_EMPTY_TILES_EN 0x00020000U |
| #define ROGUE_CR_ISP_CTL_SAMPLE_POS_SHIFT 16U |
| #define ROGUE_CR_ISP_CTL_SAMPLE_POS_CLRMSK 0xFFFEFFFFU |
| #define ROGUE_CR_ISP_CTL_SAMPLE_POS_EN 0x00010000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_SHIFT 12U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ONE 0x00000000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWO 0x00001000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THREE 0x00002000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOUR 0x00003000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIVE 0x00004000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIX 0x00005000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SEVEN 0x00006000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_EIGHT 0x00007000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_NINE 0x00008000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TEN 0x00009000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_ELEVEN 0x0000A000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_TWELVE 0x0000B000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_THIRTEEN 0x0000C000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FOURTEEN 0x0000D000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_FIFTEEN 0x0000E000U |
| #define ROGUE_CR_ISP_CTL_PIPE_ENABLE_PIPE_SIXTEEN 0x0000F000U |
| #define ROGUE_CR_ISP_CTL_VALID_ID_SHIFT 4U |
| #define ROGUE_CR_ISP_CTL_VALID_ID_CLRMSK 0xFFFFFC0FU |
| #define ROGUE_CR_ISP_CTL_UPASS_START_SHIFT 0U |
| #define ROGUE_CR_ISP_CTL_UPASS_START_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_ISP_STATUS */ |
| #define ROGUE_CR_ISP_STATUS 0x1038U |
| #define ROGUE_CR_ISP_STATUS_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_SHIFT 2U |
| #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_ISP_STATUS_SPLIT_MAX_EN 0x00000004U |
| #define ROGUE_CR_ISP_STATUS_ACTIVE_SHIFT 1U |
| #define ROGUE_CR_ISP_STATUS_ACTIVE_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_ISP_STATUS_ACTIVE_EN 0x00000002U |
| #define ROGUE_CR_ISP_STATUS_EOR_SHIFT 0U |
| #define ROGUE_CR_ISP_STATUS_EOR_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_ISP_STATUS_EOR_EN 0x00000001U |
| |
| /* Register group: ROGUE_CR_ISP_XTP_RESUME, with 64 repeats */ |
| #define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U |
| /* Register ROGUE_CR_ISP_XTP_RESUME0 */ |
| #define ROGUE_CR_ISP_XTP_RESUME0 0x3A00U |
| #define ROGUE_CR_ISP_XTP_RESUME0_MASKFULL 0x00000000003FF3FFULL |
| #define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U |
| #define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_CLRMSK 0xFFC00FFFU |
| #define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U |
| #define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_CLRMSK 0xFFFFFC00U |
| |
| /* Register group: ROGUE_CR_ISP_XTP_STORE, with 32 repeats */ |
| #define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U |
| /* Register ROGUE_CR_ISP_XTP_STORE0 */ |
| #define ROGUE_CR_ISP_XTP_STORE0 0x3C00U |
| #define ROGUE_CR_ISP_XTP_STORE0_MASKFULL 0x000000007F3FF3FFULL |
| #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U |
| #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_CLRMSK 0xBFFFFFFFU |
| #define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_EN 0x40000000U |
| #define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U |
| #define ROGUE_CR_ISP_XTP_STORE0_EOR_CLRMSK 0xDFFFFFFFU |
| #define ROGUE_CR_ISP_XTP_STORE0_EOR_EN 0x20000000U |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_EN 0x10000000U |
| #define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U |
| #define ROGUE_CR_ISP_XTP_STORE0_MT_CLRMSK 0xF0FFFFFFU |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_X_CLRMSK 0xFFC00FFFU |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U |
| #define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_CLRMSK 0xFFFFFC00U |
| |
| /* Register group: ROGUE_CR_BIF_CAT_BASE, with 8 repeats */ |
| #define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U |
| /* Register ROGUE_CR_BIF_CAT_BASE0 */ |
| #define ROGUE_CR_BIF_CAT_BASE0 0x1200U |
| #define ROGUE_CR_BIF_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE1 */ |
| #define ROGUE_CR_BIF_CAT_BASE1 0x1208U |
| #define ROGUE_CR_BIF_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE2 */ |
| #define ROGUE_CR_BIF_CAT_BASE2 0x1210U |
| #define ROGUE_CR_BIF_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE3 */ |
| #define ROGUE_CR_BIF_CAT_BASE3 0x1218U |
| #define ROGUE_CR_BIF_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE4 */ |
| #define ROGUE_CR_BIF_CAT_BASE4 0x1220U |
| #define ROGUE_CR_BIF_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE5 */ |
| #define ROGUE_CR_BIF_CAT_BASE5 0x1228U |
| #define ROGUE_CR_BIF_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE6 */ |
| #define ROGUE_CR_BIF_CAT_BASE6 0x1230U |
| #define ROGUE_CR_BIF_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE7 */ |
| #define ROGUE_CR_BIF_CAT_BASE7 0x1238U |
| #define ROGUE_CR_BIF_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_CAT_BASE_INDEX */ |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX 0x1240U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_MASKFULL 0x00070707073F0707ULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_SHIFT 48U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_RVTX_CLRMSK 0xFFF8FFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_SHIFT 40U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_RAY_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_SHIFT 32U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_HOST_CLRMSK 0xFFFFFFF8FFFFFFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_SHIFT 24U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TLA_CLRMSK 0xFFFFFFFFF8FFFFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_SHIFT 19U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TDM_CLRMSK 0xFFFFFFFFFFC7FFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_SHIFT 16U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_CDM_CLRMSK 0xFFFFFFFFFFF8FFFFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_SHIFT 8U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_PIXEL_CLRMSK 0xFFFFFFFFFFFFF8FFULL |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_SHIFT 0U |
| #define ROGUE_CR_BIF_CAT_BASE_INDEX_TA_CLRMSK 0xFFFFFFFFFFFFFFF8ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE0 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0 0x1248U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE0_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_TE0 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0 0x1250U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE0_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0 0x1260U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST0_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_VCE1 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1 0x1268U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_VCE1_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_TE1 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1 0x1270U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_TE1_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 */ |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1 0x1280U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_MASKFULL 0x0FFFFFFFFFFFF003ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_SHIFT 40U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_INIT_PAGE_CLRMSK 0xF00000FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_SHIFT 12U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_SHIFT 1U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_WRAP_EN 0x0000000000000002ULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_SHIFT 0U |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_BIF_PM_CAT_BASE_ALIST1_VALID_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_BIF_MMU_ENTRY_STATUS */ |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS 0x1288U |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_MASKFULL 0x000000FFFFFFF0F3ULL |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_SHIFT 12U |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_ADDRESS_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_SHIFT 4U |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_CAT_BASE_CLRMSK 0xFFFFFFFFFFFFFF0FULL |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_SHIFT 0U |
| #define ROGUE_CR_BIF_MMU_ENTRY_STATUS_DATA_TYPE_CLRMSK 0xFFFFFFFFFFFFFFFCULL |
| |
| /* Register ROGUE_CR_BIF_MMU_ENTRY */ |
| #define ROGUE_CR_BIF_MMU_ENTRY 0x1290U |
| #define ROGUE_CR_BIF_MMU_ENTRY_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_SHIFT 1U |
| #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_MMU_ENTRY_ENABLE_EN 0x00000002U |
| #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_SHIFT 0U |
| #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_MMU_ENTRY_PENDING_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BIF_CTRL_INVAL */ |
| #define ROGUE_CR_BIF_CTRL_INVAL 0x12A0U |
| #define ROGUE_CR_BIF_CTRL_INVAL_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_SHIFT 3U |
| #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_BIF_CTRL_INVAL_TLB1_EN 0x00000008U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PC_SHIFT 2U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_CTRL_INVAL_PC_EN 0x00000004U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PD_SHIFT 1U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_CTRL_INVAL_PD_EN 0x00000002U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PT_SHIFT 0U |
| #define ROGUE_CR_BIF_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_CTRL_INVAL_PT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BIF_CTRL */ |
| #define ROGUE_CR_BIF_CTRL 0x12A8U |
| #define ROGUE_CR_BIF_CTRL__XE_MEM__MASKFULL 0x000000000000033FULL |
| #define ROGUE_CR_BIF_CTRL_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_SHIFT 9U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_CPU_EN 0x00000200U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_SHIFT 8U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF4_EN 0x00000100U |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_SHIFT 7U |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_QUEUE_BYPASS_EN 0x00000080U |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_SHIFT 6U |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_BIF_CTRL_ENABLE_MMU_AUTO_PREFETCH_EN 0x00000040U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_SHIFT 5U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF3_EN 0x00000020U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_SHIFT 4U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF2_EN 0x00000010U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_SHIFT 3U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_BIF1_EN 0x00000008U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_SHIFT 2U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_PM_EN 0x00000004U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_SHIFT 1U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF1_EN 0x00000002U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_SHIFT 0U |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_CTRL_PAUSE_MMU_BIF0_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS */ |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS 0x12B0U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS */ |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS 0x12B8U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__MASKFULL 0x001FFFFFFFFFFFF0ULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_SHIFT 52U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__RNW_EN 0x0010000000000000ULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_SHIFT 46U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_SHIFT 40U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS__XE_MEM__TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS */ |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS 0x12C0U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_MASKFULL 0x000000000000F775ULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_SHIFT 12U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_SHIFT 8U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_SHIFT 5U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_SHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_RO_EN 0x00000010U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_SHIFT 0U |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_FAULT_BANK1_MMU_STATUS_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS */ |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS 0x12C8U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_SHIFT 50U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_RNW_EN 0x0004000000000000ULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_SHIFT 44U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_SHIFT 40U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_SHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_BANK1_REQ_STATUS_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_BIF_MMU_STATUS */ |
| #define ROGUE_CR_BIF_MMU_STATUS 0x12D0U |
| #define ROGUE_CR_BIF_MMU_STATUS__XE_MEM__MASKFULL 0x000000001FFFFFF7ULL |
| #define ROGUE_CR_BIF_MMU_STATUS_MASKFULL 0x000000001FFFFFF7ULL |
| #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_SHIFT 28U |
| #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_CLRMSK 0xEFFFFFFFU |
| #define ROGUE_CR_BIF_MMU_STATUS_PM_FAULT_EN 0x10000000U |
| #define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U |
| #define ROGUE_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU |
| #define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U |
| #define ROGUE_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU |
| #define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U |
| #define ROGUE_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU |
| #define ROGUE_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U |
| #define ROGUE_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U |
| #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U |
| #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U |
| #define ROGUE_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U |
| #define ROGUE_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U |
| |
| /* Register group: ROGUE_CR_BIF_TILING_CFG, with 8 repeats */ |
| #define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U |
| /* Register ROGUE_CR_BIF_TILING_CFG0 */ |
| #define ROGUE_CR_BIF_TILING_CFG0 0x12D8U |
| #define ROGUE_CR_BIF_TILING_CFG0_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG0_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG1 */ |
| #define ROGUE_CR_BIF_TILING_CFG1 0x12E0U |
| #define ROGUE_CR_BIF_TILING_CFG1_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG1_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG2 */ |
| #define ROGUE_CR_BIF_TILING_CFG2 0x12E8U |
| #define ROGUE_CR_BIF_TILING_CFG2_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG2_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG3 */ |
| #define ROGUE_CR_BIF_TILING_CFG3 0x12F0U |
| #define ROGUE_CR_BIF_TILING_CFG3_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG3_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG4 */ |
| #define ROGUE_CR_BIF_TILING_CFG4 0x12F8U |
| #define ROGUE_CR_BIF_TILING_CFG4_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG4_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG5 */ |
| #define ROGUE_CR_BIF_TILING_CFG5 0x1300U |
| #define ROGUE_CR_BIF_TILING_CFG5_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG5_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG6 */ |
| #define ROGUE_CR_BIF_TILING_CFG6 0x1308U |
| #define ROGUE_CR_BIF_TILING_CFG6_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG6_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_TILING_CFG7 */ |
| #define ROGUE_CR_BIF_TILING_CFG7 0x1310U |
| #define ROGUE_CR_BIF_TILING_CFG7_MASKFULL 0xFFFFFFFF0FFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U |
| #define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U |
| #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG7_ENABLE_EN 0x1000000000000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U |
| #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL |
| #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U |
| #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U |
| #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL |
| #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U |
| #define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_BIF_READS_EXT_STATUS */ |
| #define ROGUE_CR_BIF_READS_EXT_STATUS 0x1320U |
| #define ROGUE_CR_BIF_READS_EXT_STATUS_MASKFULL 0x000000000FFFFFFFULL |
| #define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_SHIFT 16U |
| #define ROGUE_CR_BIF_READS_EXT_STATUS_MMU_CLRMSK 0xF000FFFFU |
| #define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_SHIFT 0U |
| #define ROGUE_CR_BIF_READS_EXT_STATUS_BANK1_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIF_READS_INT_STATUS */ |
| #define ROGUE_CR_BIF_READS_INT_STATUS 0x1328U |
| #define ROGUE_CR_BIF_READS_INT_STATUS_MASKFULL 0x0000000007FFFFFFULL |
| #define ROGUE_CR_BIF_READS_INT_STATUS_MMU_SHIFT 16U |
| #define ROGUE_CR_BIF_READS_INT_STATUS_MMU_CLRMSK 0xF800FFFFU |
| #define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_SHIFT 0U |
| #define ROGUE_CR_BIF_READS_INT_STATUS_BANK1_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIFPM_READS_INT_STATUS */ |
| #define ROGUE_CR_BIFPM_READS_INT_STATUS 0x1330U |
| #define ROGUE_CR_BIFPM_READS_INT_STATUS_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_SHIFT 0U |
| #define ROGUE_CR_BIFPM_READS_INT_STATUS_BANK0_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIFPM_READS_EXT_STATUS */ |
| #define ROGUE_CR_BIFPM_READS_EXT_STATUS 0x1338U |
| #define ROGUE_CR_BIFPM_READS_EXT_STATUS_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_SHIFT 0U |
| #define ROGUE_CR_BIFPM_READS_EXT_STATUS_BANK0_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIFPM_STATUS_MMU */ |
| #define ROGUE_CR_BIFPM_STATUS_MMU 0x1350U |
| #define ROGUE_CR_BIFPM_STATUS_MMU_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_SHIFT 0U |
| #define ROGUE_CR_BIFPM_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_BIF_STATUS_MMU */ |
| #define ROGUE_CR_BIF_STATUS_MMU 0x1358U |
| #define ROGUE_CR_BIF_STATUS_MMU_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_SHIFT 0U |
| #define ROGUE_CR_BIF_STATUS_MMU_REQUESTS_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_BIF_FAULT_READ */ |
| #define ROGUE_CR_BIF_FAULT_READ 0x13E0U |
| #define ROGUE_CR_BIF_FAULT_READ_MASKFULL 0x000000FFFFFFFFF0ULL |
| #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_SHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSHIFT 4U |
| #define ROGUE_CR_BIF_FAULT_READ_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS */ |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS 0x1430U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_MASKFULL 0x000000000000F775ULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_SHIFT 12U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_SHIFT 8U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_SHIFT 5U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_SHIFT 4U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_RO_EN 0x00000010U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_SHIFT 0U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS */ |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS 0x1438U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_MASKFULL 0x0007FFFFFFFFFFF0ULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_SHIFT 50U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_RNW_EN 0x0004000000000000ULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_SHIFT 44U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_SB_CLRMSK 0xFFFC0FFFFFFFFFFFULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_SHIFT 40U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_SHIFT 4U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U |
| #define ROGUE_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_MCU_FENCE */ |
| #define ROGUE_CR_MCU_FENCE 0x1740U |
| #define ROGUE_CR_MCU_FENCE_MASKFULL 0x000007FFFFFFFFE0ULL |
| #define ROGUE_CR_MCU_FENCE_DM_SHIFT 40U |
| #define ROGUE_CR_MCU_FENCE_DM_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_MCU_FENCE_DM_VERTEX 0x0000000000000000ULL |
| #define ROGUE_CR_MCU_FENCE_DM_PIXEL 0x0000010000000000ULL |
| #define ROGUE_CR_MCU_FENCE_DM_COMPUTE 0x0000020000000000ULL |
| #define ROGUE_CR_MCU_FENCE_DM_RAY_VERTEX 0x0000030000000000ULL |
| #define ROGUE_CR_MCU_FENCE_DM_RAY 0x0000040000000000ULL |
| #define ROGUE_CR_MCU_FENCE_DM_FASTRENDER 0x0000050000000000ULL |
| #define ROGUE_CR_MCU_FENCE_ADDR_SHIFT 5U |
| #define ROGUE_CR_MCU_FENCE_ADDR_CLRMSK 0xFFFFFF000000001FULL |
| #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSHIFT 5U |
| #define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U |
| |
| /* Register group: ROGUE_CR_SCRATCH, with 16 repeats */ |
| #define ROGUE_CR_SCRATCH_REPEATCOUNT 16U |
| /* Register ROGUE_CR_SCRATCH0 */ |
| #define ROGUE_CR_SCRATCH0 0x1A00U |
| #define ROGUE_CR_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH1 */ |
| #define ROGUE_CR_SCRATCH1 0x1A08U |
| #define ROGUE_CR_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH2 */ |
| #define ROGUE_CR_SCRATCH2 0x1A10U |
| #define ROGUE_CR_SCRATCH2_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH2_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH3 */ |
| #define ROGUE_CR_SCRATCH3 0x1A18U |
| #define ROGUE_CR_SCRATCH3_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH3_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH4 */ |
| #define ROGUE_CR_SCRATCH4 0x1A20U |
| #define ROGUE_CR_SCRATCH4_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH4_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH5 */ |
| #define ROGUE_CR_SCRATCH5 0x1A28U |
| #define ROGUE_CR_SCRATCH5_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH5_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH6 */ |
| #define ROGUE_CR_SCRATCH6 0x1A30U |
| #define ROGUE_CR_SCRATCH6_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH6_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH7 */ |
| #define ROGUE_CR_SCRATCH7 0x1A38U |
| #define ROGUE_CR_SCRATCH7_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH7_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH8 */ |
| #define ROGUE_CR_SCRATCH8 0x1A40U |
| #define ROGUE_CR_SCRATCH8_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH8_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH9 */ |
| #define ROGUE_CR_SCRATCH9 0x1A48U |
| #define ROGUE_CR_SCRATCH9_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH9_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH10 */ |
| #define ROGUE_CR_SCRATCH10 0x1A50U |
| #define ROGUE_CR_SCRATCH10_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH10_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH11 */ |
| #define ROGUE_CR_SCRATCH11 0x1A58U |
| #define ROGUE_CR_SCRATCH11_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH11_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH12 */ |
| #define ROGUE_CR_SCRATCH12 0x1A60U |
| #define ROGUE_CR_SCRATCH12_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH12_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH13 */ |
| #define ROGUE_CR_SCRATCH13 0x1A68U |
| #define ROGUE_CR_SCRATCH13_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH13_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH14 */ |
| #define ROGUE_CR_SCRATCH14 0x1A70U |
| #define ROGUE_CR_SCRATCH14_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH14_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SCRATCH15 */ |
| #define ROGUE_CR_SCRATCH15 0x1A78U |
| #define ROGUE_CR_SCRATCH15_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U |
| #define ROGUE_CR_SCRATCH15_DATA_CLRMSK 0x00000000U |
| |
| /* Register group: ROGUE_CR_OS0_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS0_SCRATCH0 */ |
| #define ROGUE_CR_OS0_SCRATCH0 0x1A80U |
| #define ROGUE_CR_OS0_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS0_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS0_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS0_SCRATCH1 */ |
| #define ROGUE_CR_OS0_SCRATCH1 0x1A88U |
| #define ROGUE_CR_OS0_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS0_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS0_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS0_SCRATCH2 */ |
| #define ROGUE_CR_OS0_SCRATCH2 0x1A90U |
| #define ROGUE_CR_OS0_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS0_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS0_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS0_SCRATCH3 */ |
| #define ROGUE_CR_OS0_SCRATCH3 0x1A98U |
| #define ROGUE_CR_OS0_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS0_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS0_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS1_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS1_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS1_SCRATCH0 */ |
| #define ROGUE_CR_OS1_SCRATCH0 0x11A80U |
| #define ROGUE_CR_OS1_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS1_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS1_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS1_SCRATCH1 */ |
| #define ROGUE_CR_OS1_SCRATCH1 0x11A88U |
| #define ROGUE_CR_OS1_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS1_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS1_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS1_SCRATCH2 */ |
| #define ROGUE_CR_OS1_SCRATCH2 0x11A90U |
| #define ROGUE_CR_OS1_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS1_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS1_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS1_SCRATCH3 */ |
| #define ROGUE_CR_OS1_SCRATCH3 0x11A98U |
| #define ROGUE_CR_OS1_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS1_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS1_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS2_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS2_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS2_SCRATCH0 */ |
| #define ROGUE_CR_OS2_SCRATCH0 0x21A80U |
| #define ROGUE_CR_OS2_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS2_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS2_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS2_SCRATCH1 */ |
| #define ROGUE_CR_OS2_SCRATCH1 0x21A88U |
| #define ROGUE_CR_OS2_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS2_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS2_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS2_SCRATCH2 */ |
| #define ROGUE_CR_OS2_SCRATCH2 0x21A90U |
| #define ROGUE_CR_OS2_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS2_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS2_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS2_SCRATCH3 */ |
| #define ROGUE_CR_OS2_SCRATCH3 0x21A98U |
| #define ROGUE_CR_OS2_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS2_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS2_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS3_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS3_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS3_SCRATCH0 */ |
| #define ROGUE_CR_OS3_SCRATCH0 0x31A80U |
| #define ROGUE_CR_OS3_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS3_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS3_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS3_SCRATCH1 */ |
| #define ROGUE_CR_OS3_SCRATCH1 0x31A88U |
| #define ROGUE_CR_OS3_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS3_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS3_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS3_SCRATCH2 */ |
| #define ROGUE_CR_OS3_SCRATCH2 0x31A90U |
| #define ROGUE_CR_OS3_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS3_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS3_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS3_SCRATCH3 */ |
| #define ROGUE_CR_OS3_SCRATCH3 0x31A98U |
| #define ROGUE_CR_OS3_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS3_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS3_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS4_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS4_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS4_SCRATCH0 */ |
| #define ROGUE_CR_OS4_SCRATCH0 0x41A80U |
| #define ROGUE_CR_OS4_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS4_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS4_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS4_SCRATCH1 */ |
| #define ROGUE_CR_OS4_SCRATCH1 0x41A88U |
| #define ROGUE_CR_OS4_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS4_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS4_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS4_SCRATCH2 */ |
| #define ROGUE_CR_OS4_SCRATCH2 0x41A90U |
| #define ROGUE_CR_OS4_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS4_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS4_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS4_SCRATCH3 */ |
| #define ROGUE_CR_OS4_SCRATCH3 0x41A98U |
| #define ROGUE_CR_OS4_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS4_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS4_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS5_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS5_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS5_SCRATCH0 */ |
| #define ROGUE_CR_OS5_SCRATCH0 0x51A80U |
| #define ROGUE_CR_OS5_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS5_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS5_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS5_SCRATCH1 */ |
| #define ROGUE_CR_OS5_SCRATCH1 0x51A88U |
| #define ROGUE_CR_OS5_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS5_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS5_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS5_SCRATCH2 */ |
| #define ROGUE_CR_OS5_SCRATCH2 0x51A90U |
| #define ROGUE_CR_OS5_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS5_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS5_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS5_SCRATCH3 */ |
| #define ROGUE_CR_OS5_SCRATCH3 0x51A98U |
| #define ROGUE_CR_OS5_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS5_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS5_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS6_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS6_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS6_SCRATCH0 */ |
| #define ROGUE_CR_OS6_SCRATCH0 0x61A80U |
| #define ROGUE_CR_OS6_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS6_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS6_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS6_SCRATCH1 */ |
| #define ROGUE_CR_OS6_SCRATCH1 0x61A88U |
| #define ROGUE_CR_OS6_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS6_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS6_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS6_SCRATCH2 */ |
| #define ROGUE_CR_OS6_SCRATCH2 0x61A90U |
| #define ROGUE_CR_OS6_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS6_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS6_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS6_SCRATCH3 */ |
| #define ROGUE_CR_OS6_SCRATCH3 0x61A98U |
| #define ROGUE_CR_OS6_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS6_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS6_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register group: ROGUE_CR_OS7_SCRATCH, with 2 repeats */ |
| #define ROGUE_CR_OS7_SCRATCH_REPEATCOUNT 2U |
| /* Register ROGUE_CR_OS7_SCRATCH0 */ |
| #define ROGUE_CR_OS7_SCRATCH0 0x71A80U |
| #define ROGUE_CR_OS7_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS7_SCRATCH0_DATA_SHIFT 0U |
| #define ROGUE_CR_OS7_SCRATCH0_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS7_SCRATCH1 */ |
| #define ROGUE_CR_OS7_SCRATCH1 0x71A88U |
| #define ROGUE_CR_OS7_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_OS7_SCRATCH1_DATA_SHIFT 0U |
| #define ROGUE_CR_OS7_SCRATCH1_DATA_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OS7_SCRATCH2 */ |
| #define ROGUE_CR_OS7_SCRATCH2 0x71A90U |
| #define ROGUE_CR_OS7_SCRATCH2_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS7_SCRATCH2_DATA_SHIFT 0U |
| #define ROGUE_CR_OS7_SCRATCH2_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_OS7_SCRATCH3 */ |
| #define ROGUE_CR_OS7_SCRATCH3 0x71A98U |
| #define ROGUE_CR_OS7_SCRATCH3_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_OS7_SCRATCH3_DATA_SHIFT 0U |
| #define ROGUE_CR_OS7_SCRATCH3_DATA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR */ |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR 0x2700U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_SHIFT 0U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_CLRMSK 0xFFFF0000U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSHIFT 4U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_SIZE_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN */ |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN 0x2708U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_MASKFULL 0x000000FFFFFFFFF0ULL |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_SHIFT 4U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSHIFT 4U |
| #define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U |
| |
| /* Register group: ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 0x3000U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 0x3008U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 0x3010U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 0x3018U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 0x3020U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 0x3028U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 0x3030U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 0x3038U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 0x3040U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 0x3048U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 0x3050U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 0x3058U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 0x3060U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 0x3068U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 0x3070U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 */ |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 0x3078U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL 0x7FFFF7FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_EN 0x4000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN 0x2000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN 0x1000000000000000ULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_BOOT */ |
| #define ROGUE_CR_FWCORE_BOOT 0x3090U |
| #define ROGUE_CR_FWCORE_BOOT_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_FWCORE_BOOT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_FWCORE_BOOT_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_BOOT_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_RESET_ADDR */ |
| #define ROGUE_CR_FWCORE_RESET_ADDR 0x3098U |
| #define ROGUE_CR_FWCORE_RESET_ADDR_MASKFULL 0x00000000FFFFFFFEULL |
| #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_SHIFT 1U |
| #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_CLRMSK 0x00000001U |
| #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSHIFT 1U |
| #define ROGUE_CR_FWCORE_RESET_ADDR_ADDR_ALIGNSIZE 2U |
| |
| /* Register ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR */ |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR 0x30A0U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_MASKFULL 0x00000000FFFFFFFEULL |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_SHIFT 1U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_CLRMSK 0x00000001U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSHIFT 1U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_ADDR_ADDR_ALIGNSIZE 2U |
| |
| /* Register ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT */ |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT 0x30A8U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_SHIFT 0U |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_WRAPPER_NMI_EVENT_TRIGGER_EN_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS */ |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS 0x30B0U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_MASKFULL 0x000000000000F771ULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_SHIFT 8U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_SHIFT 5U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_SHIFT 4U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_RO_EN 0x00000010U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_SHIFT 0U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_MEM_FAULT_MMU_STATUS_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS */ |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS 0x30B8U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_MASKFULL 0x001FFFFFFFFFFFF0ULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_SHIFT 52U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_CLRMSK 0xFFEFFFFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_RNW_EN 0x0010000000000000ULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_SHIFT 46U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_SB_CLRMSK 0xFFF03FFFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_SHIFT 40U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFC0FFFFFFFFFFULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_SHIFT 4U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U |
| #define ROGUE_CR_FWCORE_MEM_FAULT_REQ_STATUS_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CTRL_INVAL */ |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL 0x30C0U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_SHIFT 3U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_TLB_EN 0x00000008U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_SHIFT 2U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PC_EN 0x00000004U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_SHIFT 1U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PD_EN 0x00000002U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_SHIFT 0U |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_MEM_CTRL_INVAL_PT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_MMU_STATUS */ |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS 0x30C8U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_SHIFT 20U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_SHIFT 4U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_SHIFT 2U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_STALLED_EN 0x00000004U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_SHIFT 1U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_PAUSED_EN 0x00000002U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_SHIFT 0U |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_MEM_MMU_STATUS_BUSY_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS */ |
| #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS 0x30D8U |
| #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MASKFULL 0x0000000000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_SHIFT 0U |
| #define ROGUE_CR_FWCORE_MEM_READS_EXT_STATUS_MMU_CLRMSK 0xFFFFF000U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_READS_INT_STATUS */ |
| #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS 0x30E0U |
| #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MASKFULL 0x00000000000007FFULL |
| #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_SHIFT 0U |
| #define ROGUE_CR_FWCORE_MEM_READS_INT_STATUS_MMU_CLRMSK 0xFFFFF800U |
| |
| /* Register ROGUE_CR_FWCORE_WRAPPER_FENCE */ |
| #define ROGUE_CR_FWCORE_WRAPPER_FENCE 0x30E8U |
| #define ROGUE_CR_FWCORE_WRAPPER_FENCE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_SHIFT 0U |
| #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_EN 0x00000001U |
| |
| /* Register group: ROGUE_CR_FWCORE_MEM_CAT_BASE, with 8 repeats */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE0 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0 0x30F0U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE1 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1 0x30F8U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE2 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2 0x3100U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE3 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3 0x3108U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE4 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4 0x3110U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE5 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5 0x3118U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE6 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6 0x3120U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_MEM_CAT_BASE7 */ |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7 0x3128U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_FWCORE_WDT_RESET */ |
| #define ROGUE_CR_FWCORE_WDT_RESET 0x3130U |
| #define ROGUE_CR_FWCORE_WDT_RESET_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_FWCORE_WDT_RESET_EN_SHIFT 0U |
| #define ROGUE_CR_FWCORE_WDT_RESET_EN_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_WDT_RESET_EN_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_WDT_CTRL */ |
| #define ROGUE_CR_FWCORE_WDT_CTRL 0x3138U |
| #define ROGUE_CR_FWCORE_WDT_CTRL_MASKFULL 0x00000000FFFF1F01ULL |
| #define ROGUE_CR_FWCORE_WDT_CTRL_PROT_SHIFT 16U |
| #define ROGUE_CR_FWCORE_WDT_CTRL_PROT_CLRMSK 0x0000FFFFU |
| #define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_SHIFT 8U |
| #define ROGUE_CR_FWCORE_WDT_CTRL_THRESHOLD_CLRMSK 0xFFFFE0FFU |
| #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_FWCORE_WDT_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FWCORE_WDT_COUNT */ |
| #define ROGUE_CR_FWCORE_WDT_COUNT 0x3140U |
| #define ROGUE_CR_FWCORE_WDT_COUNT_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_SHIFT 0U |
| #define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK 0x00000000U |
| |
| /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED0, with 4 repeats */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED00 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED00 0x3400U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED00_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED01 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED01 0x3408U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED01_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED02 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED02 0x3410U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED02_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED03 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED03 0x3418U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED03_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_DATA0 */ |
| #define ROGUE_CR_FWCORE_DMI_DATA0 0x3420U |
| #define ROGUE_CR_FWCORE_DMI_DATA0_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_DATA1 */ |
| #define ROGUE_CR_FWCORE_DMI_DATA1 0x3428U |
| #define ROGUE_CR_FWCORE_DMI_DATA1_MASKFULL 0x0000000000000000ULL |
| |
| /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED1, with 5 repeats */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED10 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED10 0x3430U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED10_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED11 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED11 0x3438U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED11_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED12 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED12 0x3440U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED12_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED13 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED13 0x3448U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED13_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED14 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED14 0x3450U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED14_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */ |
| #define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U |
| #define ROGUE_CR_FWCORE_DMI_DMCONTROL_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_DMSTATUS */ |
| #define ROGUE_CR_FWCORE_DMI_DMSTATUS 0x3488U |
| #define ROGUE_CR_FWCORE_DMI_DMSTATUS_MASKFULL 0x0000000000000000ULL |
| |
| /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED2, with 4 repeats */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED20 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED20 0x3490U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED20_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED21 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED21 0x3498U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED21_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED22 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED22 0x34A0U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED22_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED23 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED23 0x34A8U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED23_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_ABSTRACTCS */ |
| #define ROGUE_CR_FWCORE_DMI_ABSTRACTCS 0x34B0U |
| #define ROGUE_CR_FWCORE_DMI_ABSTRACTCS_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_COMMAND */ |
| #define ROGUE_CR_FWCORE_DMI_COMMAND 0x34B8U |
| #define ROGUE_CR_FWCORE_DMI_COMMAND_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_SBCS */ |
| #define ROGUE_CR_FWCORE_DMI_SBCS 0x35C0U |
| #define ROGUE_CR_FWCORE_DMI_SBCS_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_SBADDRESS0 */ |
| #define ROGUE_CR_FWCORE_DMI_SBADDRESS0 0x35C8U |
| #define ROGUE_CR_FWCORE_DMI_SBADDRESS0_MASKFULL 0x0000000000000000ULL |
| |
| /* Register group: ROGUE_CR_FWCORE_DMI_RESERVED3, with 2 repeats */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED30 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED30 0x34D0U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED30_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_RESERVED31 */ |
| #define ROGUE_CR_FWCORE_DMI_RESERVED31 0x34D8U |
| #define ROGUE_CR_FWCORE_DMI_RESERVED31_MASKFULL 0x0000000000000000ULL |
| |
| /* Register group: ROGUE_CR_FWCORE_DMI_SBDATA, with 4 repeats */ |
| #define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U |
| /* Register ROGUE_CR_FWCORE_DMI_SBDATA0 */ |
| #define ROGUE_CR_FWCORE_DMI_SBDATA0 0x35E0U |
| #define ROGUE_CR_FWCORE_DMI_SBDATA0_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_SBDATA1 */ |
| #define ROGUE_CR_FWCORE_DMI_SBDATA1 0x35E8U |
| #define ROGUE_CR_FWCORE_DMI_SBDATA1_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_SBDATA2 */ |
| #define ROGUE_CR_FWCORE_DMI_SBDATA2 0x35F0U |
| #define ROGUE_CR_FWCORE_DMI_SBDATA2_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_SBDATA3 */ |
| #define ROGUE_CR_FWCORE_DMI_SBDATA3 0x35F8U |
| #define ROGUE_CR_FWCORE_DMI_SBDATA3_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_FWCORE_DMI_HALTSUM0 */ |
| #define ROGUE_CR_FWCORE_DMI_HALTSUM0 0x3600U |
| #define ROGUE_CR_FWCORE_DMI_HALTSUM0_MASKFULL 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_SLC_CTRL_MISC */ |
| #define ROGUE_CR_SLC_CTRL_MISC 0x3800U |
| #define ROGUE_CR_SLC_CTRL_MISC_MASKFULL 0xFFFFFFFF01FF010FULL |
| #define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_SHIFT 32U |
| #define ROGUE_CR_SLC_CTRL_MISC_SCRAMBLE_BITS_CLRMSK 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_SHIFT 24U |
| #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_CLRMSK 0xFFFFFFFFFEFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN 0x0000000001000000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 16U |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFFFFF00FFFFULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_64_BYTE 0x0000000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_INTERLEAVED_128_BYTE 0x0000000000010000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH1 0x0000000000100000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_SIMPLE_HASH2 0x0000000000110000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH1 0x0000000000200000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ADDR_DECODE_MODE_PVR_HASH2_SCRAMBLE 0x0000000000210000ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_SHIFT 8U |
| #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_SLC_CTRL_MISC_PAUSE_EN 0x0000000000000100ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_SHIFT 3U |
| #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_RESP_PRIORITY_EN 0x0000000000000008ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_SHIFT 2U |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_LINE_USE_LIMIT_EN 0x0000000000000004ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_SHIFT 1U |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_SLC_CTRL_MISC_ENABLE_PSG_HAZARD_CHECK_EN 0x0000000000000002ULL |
| #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_SHIFT 0U |
| #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_SLC_CTRL_FLUSH_INVAL */ |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL 0x3818U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_MASKFULL 0x0000000080000FFFULL |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_SHIFT 31U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_CLRMSK 0x7FFFFFFFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_LAZY_EN 0x80000000U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_SHIFT 11U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_CLRMSK 0xFFFFF7FFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FASTRENDER_EN 0x00000800U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_SHIFT 10U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_CLRMSK 0xFFFFFBFFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_VERTEX_EN 0x00000400U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_SHIFT 9U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_RAY_EN 0x00000200U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_SHIFT 8U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_FRC_EN 0x00000100U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_SHIFT 7U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXE_EN 0x00000080U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_SHIFT 6U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_VXD_EN 0x00000040U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_SHIFT 5U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_HOST_META_EN 0x00000020U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_SHIFT 4U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_MMU_EN 0x00000010U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_SHIFT 3U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_COMPUTE_EN 0x00000008U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_SHIFT 2U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_PIXEL_EN 0x00000004U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_SHIFT 1U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_DM_TA_EN 0x00000002U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_SHIFT 0U |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SLC_CTRL_FLUSH_INVAL_ALL_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SLC_STATUS0 */ |
| #define ROGUE_CR_SLC_STATUS0 0x3820U |
| #define ROGUE_CR_SLC_STATUS0_MASKFULL 0x0000000000000007ULL |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_SHIFT 2U |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_INVAL_PENDING_EN 0x00000004U |
| #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_SHIFT 1U |
| #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SLC_STATUS0_INVAL_PENDING_EN 0x00000002U |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_SHIFT 0U |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SLC_STATUS0_FLUSH_PENDING_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SLC_CTRL_BYPASS */ |
| #define ROGUE_CR_SLC_CTRL_BYPASS 0x3828U |
| #define ROGUE_CR_SLC_CTRL_BYPASS__XE_MEM__MASKFULL 0x0FFFFFFFFFFF7FFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_MASKFULL 0x000000000FFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_SHIFT 59U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_CLRMSK 0xF7FFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_ZLS_EN 0x0800000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_SHIFT 58U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_CLRMSK 0xFBFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_HEADER_EN 0x0400000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_SHIFT 57U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_CLRMSK 0xFDFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_HEADER_EN 0x0200000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_SHIFT 56U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_CLRMSK 0xFEFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_ZLS_DATA_EN 0x0100000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_SHIFT 55U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_CLRMSK 0xFF7FFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_DECOMP_TCU_DATA_EN 0x0080000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_SHIFT 54U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_CLRMSK 0xFFBFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TFBC_COMP_PBE_EN 0x0040000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_SHIFT 53U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_CLRMSK 0xFFDFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_DM_COMPUTE_EN 0x0020000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_SHIFT 52U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_CLRMSK 0xFFEFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PDSRW_NOLINEFILL_EN 0x0010000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_SHIFT 51U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_CLRMSK 0xFFF7FFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_PBE_NOLINEFILL_EN 0x0008000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_SHIFT 50U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBC_EN 0x0004000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_SHIFT 49U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_CLRMSK 0xFFFDFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_RREQ_EN 0x0002000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_SHIFT 48U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_CLRMSK 0xFFFEFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CREQ_EN 0x0001000000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_SHIFT 47U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_CLRMSK 0xFFFF7FFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_PREQ_EN 0x0000800000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_SHIFT 46U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_CLRMSK 0xFFFFBFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_DBSC_EN 0x0000400000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_SHIFT 45U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_CLRMSK 0xFFFFDFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TCU_EN 0x0000200000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_SHIFT 44U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_CLRMSK 0xFFFFEFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PBE_EN 0x0000100000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_SHIFT 43U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_CLRMSK 0xFFFFF7FFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_ISP_EN 0x0000080000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_SHIFT 42U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_CLRMSK 0xFFFFFBFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PM_EN 0x0000040000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_SHIFT 41U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_CLRMSK 0xFFFFFDFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TDM_EN 0x0000020000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_SHIFT 40U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_CLRMSK 0xFFFFFEFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_CDM_EN 0x0000010000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_SHIFT 39U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_CLRMSK 0xFFFFFF7FFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_PDS_STATE_EN 0x0000008000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_SHIFT 38U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_CLRMSK 0xFFFFFFBFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_DB_EN 0x0000004000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_SHIFT 37U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_CLRMSK 0xFFFFFFDFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TSPF_VTX_VAR_EN 0x0000002000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_SHIFT 36U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_CLRMSK 0xFFFFFFEFFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_VDM_EN 0x0000001000000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_SHIFT 35U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_CLRMSK 0xFFFFFFF7FFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_STREAM_EN 0x0000000800000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_SHIFT 34U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_CLRMSK 0xFFFFFFFBFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PSG_REGION_EN 0x0000000400000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_SHIFT 33U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_CLRMSK 0xFFFFFFFDFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_VCE_EN 0x0000000200000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_SHIFT 32U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_PPP_EN 0x0000000100000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_SHIFT 31U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FASTRENDER_EN 0x0000000080000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_SHIFT 30U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_CLRMSK 0xFFFFFFFFBFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PM_ALIST_EN 0x0000000040000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_SHIFT 29U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_CLRMSK 0xFFFFFFFFDFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_TE_EN 0x0000000020000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_SHIFT 28U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_CLRMSK 0xFFFFFFFFEFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PB_VCE_EN 0x0000000010000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_SHIFT 27U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_CLRMSK 0xFFFFFFFFF7FFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_VERTEX_EN 0x0000000008000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_SHIFT 26U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_CLRMSK 0xFFFFFFFFFBFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_RAY_EN 0x0000000004000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_SHIFT 25U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_CLRMSK 0xFFFFFFFFFDFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_CPF_EN 0x0000000002000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_SHIFT 24U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_CLRMSK 0xFFFFFFFFFEFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPU_EN 0x0000000001000000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_SHIFT 23U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_CLRMSK 0xFFFFFFFFFF7FFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_FBDC_EN 0x0000000000800000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_SHIFT 22U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_CLRMSK 0xFFFFFFFFFFBFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TLA_EN 0x0000000000400000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_SHIFT 21U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_N_EN 0x0000000000200000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_SHIFT 20U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_CLRMSK 0xFFFFFFFFFFEFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_BYP_CC_EN 0x0000000000100000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_SHIFT 19U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_CLRMSK 0xFFFFFFFFFFF7FFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MCU_EN 0x0000000000080000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_SHIFT 18U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_CLRMSK 0xFFFFFFFFFFFBFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_PDS_EN 0x0000000000040000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_SHIFT 17U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_CLRMSK 0xFFFFFFFFFFFDFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TPF_EN 0x0000000000020000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_SHIFT 16U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_CLRMSK 0xFFFFFFFFFFFEFFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_TA_TPC_EN 0x0000000000010000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_SHIFT 15U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_CLRMSK 0xFFFFFFFFFFFF7FFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_IPF_OBJ_EN 0x0000000000008000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_SHIFT 14U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_CLRMSK 0xFFFFFFFFFFFFBFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_USC_EN 0x0000000000004000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_SHIFT 13U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_CLRMSK 0xFFFFFFFFFFFFDFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_META_EN 0x0000000000002000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_SHIFT 12U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_CLRMSK 0xFFFFFFFFFFFFEFFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_HOST_EN 0x0000000000001000ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_SHIFT 11U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_CLRMSK 0xFFFFFFFFFFFFF7FFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PT_EN 0x0000000000000800ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_SHIFT 10U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PD_EN 0x0000000000000400ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_SHIFT 9U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_CLRMSK 0xFFFFFFFFFFFFFDFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_REQ_MMU_PC_EN 0x0000000000000200ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_SHIFT 8U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_FRC_EN 0x0000000000000100ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_SHIFT 7U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_CLRMSK 0xFFFFFFFFFFFFFF7FULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXE_EN 0x0000000000000080ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_SHIFT 6U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_CLRMSK 0xFFFFFFFFFFFFFFBFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_VXD_EN 0x0000000000000040ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_SHIFT 5U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_HOST_META_EN 0x0000000000000020ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_SHIFT 4U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_MMU_EN 0x0000000000000010ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_SHIFT 3U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_COMPUTE_EN 0x0000000000000008ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_SHIFT 2U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_PIXEL_EN 0x0000000000000004ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_SHIFT 1U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_DM_TA_EN 0x0000000000000002ULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_SHIFT 0U |
| #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_SLC_CTRL_BYPASS_ALL_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_SLC_STATUS1 */ |
| #define ROGUE_CR_SLC_STATUS1 0x3870U |
| #define ROGUE_CR_SLC_STATUS1_MASKFULL 0x800003FF03FFFFFFULL |
| #define ROGUE_CR_SLC_STATUS1_PAUSED_SHIFT 63U |
| #define ROGUE_CR_SLC_STATUS1_PAUSED_CLRMSK 0x7FFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC_STATUS1_PAUSED_EN 0x8000000000000000ULL |
| #define ROGUE_CR_SLC_STATUS1_READS1_SHIFT 32U |
| #define ROGUE_CR_SLC_STATUS1_READS1_CLRMSK 0xFFFFFC00FFFFFFFFULL |
| #define ROGUE_CR_SLC_STATUS1_READS0_SHIFT 16U |
| #define ROGUE_CR_SLC_STATUS1_READS0_CLRMSK 0xFFFFFFFFFC00FFFFULL |
| #define ROGUE_CR_SLC_STATUS1_READS1_EXT_SHIFT 8U |
| #define ROGUE_CR_SLC_STATUS1_READS1_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL |
| #define ROGUE_CR_SLC_STATUS1_READS0_EXT_SHIFT 0U |
| #define ROGUE_CR_SLC_STATUS1_READS0_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL |
| |
| /* Register ROGUE_CR_SLC_IDLE */ |
| #define ROGUE_CR_SLC_IDLE 0x3898U |
| #define ROGUE_CR_SLC_IDLE__XE_MEM__MASKFULL 0x00000000000003FFULL |
| #define ROGUE_CR_SLC_IDLE_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_SHIFT 9U |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB1_EN 0x00000200U |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_SHIFT 8U |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_SLC_IDLE_MH_SYSARB0_EN 0x00000100U |
| #define ROGUE_CR_SLC_IDLE_IMGBV4_SHIFT 7U |
| #define ROGUE_CR_SLC_IDLE_IMGBV4_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_SLC_IDLE_IMGBV4_EN 0x00000080U |
| #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_SHIFT 6U |
| #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SLC_IDLE_CACHE_BANKS_EN 0x00000040U |
| #define ROGUE_CR_SLC_IDLE_RBOFIFO_SHIFT 5U |
| #define ROGUE_CR_SLC_IDLE_RBOFIFO_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SLC_IDLE_RBOFIFO_EN 0x00000020U |
| #define ROGUE_CR_SLC_IDLE_FRC_CONV_SHIFT 4U |
| #define ROGUE_CR_SLC_IDLE_FRC_CONV_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SLC_IDLE_FRC_CONV_EN 0x00000010U |
| #define ROGUE_CR_SLC_IDLE_VXE_CONV_SHIFT 3U |
| #define ROGUE_CR_SLC_IDLE_VXE_CONV_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SLC_IDLE_VXE_CONV_EN 0x00000008U |
| #define ROGUE_CR_SLC_IDLE_VXD_CONV_SHIFT 2U |
| #define ROGUE_CR_SLC_IDLE_VXD_CONV_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SLC_IDLE_VXD_CONV_EN 0x00000004U |
| #define ROGUE_CR_SLC_IDLE_BIF1_CONV_SHIFT 1U |
| #define ROGUE_CR_SLC_IDLE_BIF1_CONV_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SLC_IDLE_BIF1_CONV_EN 0x00000002U |
| #define ROGUE_CR_SLC_IDLE_CBAR_SHIFT 0U |
| #define ROGUE_CR_SLC_IDLE_CBAR_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SLC_IDLE_CBAR_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SLC_STATUS2 */ |
| #define ROGUE_CR_SLC_STATUS2 0x3908U |
| #define ROGUE_CR_SLC_STATUS2_MASKFULL 0x000003FF03FFFFFFULL |
| #define ROGUE_CR_SLC_STATUS2_READS3_SHIFT 32U |
| #define ROGUE_CR_SLC_STATUS2_READS3_CLRMSK 0xFFFFFC00FFFFFFFFULL |
| #define ROGUE_CR_SLC_STATUS2_READS2_SHIFT 16U |
| #define ROGUE_CR_SLC_STATUS2_READS2_CLRMSK 0xFFFFFFFFFC00FFFFULL |
| #define ROGUE_CR_SLC_STATUS2_READS3_EXT_SHIFT 8U |
| #define ROGUE_CR_SLC_STATUS2_READS3_EXT_CLRMSK 0xFFFFFFFFFFFF00FFULL |
| #define ROGUE_CR_SLC_STATUS2_READS2_EXT_SHIFT 0U |
| #define ROGUE_CR_SLC_STATUS2_READS2_EXT_CLRMSK 0xFFFFFFFFFFFFFF00ULL |
| |
| /* Register ROGUE_CR_SLC_CTRL_MISC2 */ |
| #define ROGUE_CR_SLC_CTRL_MISC2 0x3930U |
| #define ROGUE_CR_SLC_CTRL_MISC2_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_SHIFT 0U |
| #define ROGUE_CR_SLC_CTRL_MISC2_SCRAMBLE_BITS_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE */ |
| #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE 0x3938U |
| #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_SHIFT 0U |
| #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SLC_CROSSBAR_LOAD_BALANCE_BYPASS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_USC_UVS0_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS0_CHECKSUM 0x5000U |
| #define ROGUE_CR_USC_UVS0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS0_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVS1_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS1_CHECKSUM 0x5008U |
| #define ROGUE_CR_USC_UVS1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS1_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVS2_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS2_CHECKSUM 0x5010U |
| #define ROGUE_CR_USC_UVS2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS2_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVS3_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS3_CHECKSUM 0x5018U |
| #define ROGUE_CR_USC_UVS3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS3_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PPP_SIGNATURE */ |
| #define ROGUE_CR_PPP_SIGNATURE 0x5020U |
| #define ROGUE_CR_PPP_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PPP_SIGNATURE_VALUE_SHIFT 0U |
| #define ROGUE_CR_PPP_SIGNATURE_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TE_SIGNATURE */ |
| #define ROGUE_CR_TE_SIGNATURE 0x5028U |
| #define ROGUE_CR_TE_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TE_SIGNATURE_VALUE_SHIFT 0U |
| #define ROGUE_CR_TE_SIGNATURE_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TE_CHECKSUM */ |
| #define ROGUE_CR_TE_CHECKSUM 0x5110U |
| #define ROGUE_CR_TE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TE_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_TE_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVB_CHECKSUM */ |
| #define ROGUE_CR_USC_UVB_CHECKSUM 0x5118U |
| #define ROGUE_CR_USC_UVB_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVB_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_VCE_CHECKSUM */ |
| #define ROGUE_CR_VCE_CHECKSUM 0x5030U |
| #define ROGUE_CR_VCE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_VCE_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_VCE_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_ISP_PDS_CHECKSUM */ |
| #define ROGUE_CR_ISP_PDS_CHECKSUM 0x5038U |
| #define ROGUE_CR_ISP_PDS_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_ISP_PDS_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_ISP_TPF_CHECKSUM */ |
| #define ROGUE_CR_ISP_TPF_CHECKSUM 0x5040U |
| #define ROGUE_CR_ISP_TPF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_ISP_TPF_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TFPU_PLANE0_CHECKSUM */ |
| #define ROGUE_CR_TFPU_PLANE0_CHECKSUM 0x5048U |
| #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_TFPU_PLANE0_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TFPU_PLANE1_CHECKSUM */ |
| #define ROGUE_CR_TFPU_PLANE1_CHECKSUM 0x5050U |
| #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_TFPU_PLANE1_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PBE_CHECKSUM */ |
| #define ROGUE_CR_PBE_CHECKSUM 0x5058U |
| #define ROGUE_CR_PBE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PBE_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_PBE_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PDS_DOUTM_STM_SIGNATURE */ |
| #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE 0x5060U |
| #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_SHIFT 0U |
| #define ROGUE_CR_PDS_DOUTM_STM_SIGNATURE_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_IFPU_ISP_CHECKSUM */ |
| #define ROGUE_CR_IFPU_ISP_CHECKSUM 0x5068U |
| #define ROGUE_CR_IFPU_ISP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_IFPU_ISP_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVS4_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS4_CHECKSUM 0x5100U |
| #define ROGUE_CR_USC_UVS4_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS4_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_UVS5_CHECKSUM */ |
| #define ROGUE_CR_USC_UVS5_CHECKSUM 0x5108U |
| #define ROGUE_CR_USC_UVS5_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_USC_UVS5_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PPP_CLIP_CHECKSUM */ |
| #define ROGUE_CR_PPP_CLIP_CHECKSUM 0x5120U |
| #define ROGUE_CR_PPP_CLIP_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_PPP_CLIP_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_TA_PHASE */ |
| #define ROGUE_CR_PERF_TA_PHASE 0x6008U |
| #define ROGUE_CR_PERF_TA_PHASE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_TA_PHASE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_TA_PHASE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_3D_PHASE */ |
| #define ROGUE_CR_PERF_3D_PHASE 0x6010U |
| #define ROGUE_CR_PERF_3D_PHASE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_3D_PHASE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_3D_PHASE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_COMPUTE_PHASE */ |
| #define ROGUE_CR_PERF_COMPUTE_PHASE 0x6018U |
| #define ROGUE_CR_PERF_COMPUTE_PHASE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_COMPUTE_PHASE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_TA_CYCLE */ |
| #define ROGUE_CR_PERF_TA_CYCLE 0x6020U |
| #define ROGUE_CR_PERF_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_TA_CYCLE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_TA_CYCLE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_3D_CYCLE */ |
| #define ROGUE_CR_PERF_3D_CYCLE 0x6028U |
| #define ROGUE_CR_PERF_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_3D_CYCLE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_3D_CYCLE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_COMPUTE_CYCLE */ |
| #define ROGUE_CR_PERF_COMPUTE_CYCLE 0x6030U |
| #define ROGUE_CR_PERF_COMPUTE_CYCLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_COMPUTE_CYCLE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_TA_OR_3D_CYCLE */ |
| #define ROGUE_CR_PERF_TA_OR_3D_CYCLE 0x6038U |
| #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_TA_OR_3D_CYCLE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_INITIAL_TA_CYCLE */ |
| #define ROGUE_CR_PERF_INITIAL_TA_CYCLE 0x6040U |
| #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_INITIAL_TA_CYCLE_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC0_READ_STALL */ |
| #define ROGUE_CR_PERF_SLC0_READ_STALL 0x60B8U |
| #define ROGUE_CR_PERF_SLC0_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC0_READ_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC0_WRITE_STALL */ |
| #define ROGUE_CR_PERF_SLC0_WRITE_STALL 0x60C0U |
| #define ROGUE_CR_PERF_SLC0_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC0_WRITE_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC1_READ_STALL */ |
| #define ROGUE_CR_PERF_SLC1_READ_STALL 0x60E0U |
| #define ROGUE_CR_PERF_SLC1_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC1_READ_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC1_WRITE_STALL */ |
| #define ROGUE_CR_PERF_SLC1_WRITE_STALL 0x60E8U |
| #define ROGUE_CR_PERF_SLC1_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC1_WRITE_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC2_READ_STALL */ |
| #define ROGUE_CR_PERF_SLC2_READ_STALL 0x6158U |
| #define ROGUE_CR_PERF_SLC2_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC2_READ_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC2_WRITE_STALL */ |
| #define ROGUE_CR_PERF_SLC2_WRITE_STALL 0x6160U |
| #define ROGUE_CR_PERF_SLC2_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC2_WRITE_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC3_READ_STALL */ |
| #define ROGUE_CR_PERF_SLC3_READ_STALL 0x6180U |
| #define ROGUE_CR_PERF_SLC3_READ_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC3_READ_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_SLC3_WRITE_STALL */ |
| #define ROGUE_CR_PERF_SLC3_WRITE_STALL 0x6188U |
| #define ROGUE_CR_PERF_SLC3_WRITE_STALL_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_SHIFT 0U |
| #define ROGUE_CR_PERF_SLC3_WRITE_STALL_COUNT_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PERF_3D_SPINUP */ |
| #define ROGUE_CR_PERF_3D_SPINUP 0x6220U |
| #define ROGUE_CR_PERF_3D_SPINUP_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PERF_3D_SPINUP_CYCLES_SHIFT 0U |
| #define ROGUE_CR_PERF_3D_SPINUP_CYCLES_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_AXI_ACE_LITE_CONFIGURATION */ |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION 0x38C0U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_MASKFULL 0x00003FFFFFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_SHIFT 45U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_CLRMSK 0xFFFFDFFFFFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ENABLE_FENCE_OUT_EN 0x0000200000000000ULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_SHIFT 37U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_OSID_SECURITY_CLRMSK 0xFFFFE01FFFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_SHIFT 36U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_CLRMSK \ |
| 0xFFFFFFEFFFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITELINEUNIQUE_EN \ |
| 0x0000001000000000ULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_SHIFT 35U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_CLRMSK 0xFFFFFFF7FFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_WRITE_EN 0x0000000800000000ULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_SHIFT 34U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_CLRMSK 0xFFFFFFFBFFFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_DISABLE_COHERENT_READ_EN 0x0000000400000000ULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_SHIFT 30U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFC3FFFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_SHIFT 26U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_COHERENT_CLRMSK 0xFFFFFFFFC3FFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_SHIFT 22U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_COHERENT_CLRMSK 0xFFFFFFFFFC3FFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_SHIFT 20U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFCFFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_SHIFT 18U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_BARRIER_CLRMSK 0xFFFFFFFFFFF3FFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_SHIFT 16U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_CACHE_MAINTENANCE_CLRMSK 0xFFFFFFFFFFFCFFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_SHIFT 14U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFF3FFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_SHIFT 12U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_COHERENT_CLRMSK 0xFFFFFFFFFFFFCFFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_SHIFT 10U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFF3FFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_SHIFT 8U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWDOMAIN_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFCFFULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_SHIFT 4U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_ARCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFF0FULL |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_SHIFT 0U |
| #define ROGUE_CR_AXI_ACE_LITE_CONFIGURATION_AWCACHE_NON_SNOOPING_CLRMSK 0xFFFFFFFFFFFFFFF0ULL |
| |
| /* Register ROGUE_CR_POWER_ESTIMATE_RESULT */ |
| #define ROGUE_CR_POWER_ESTIMATE_RESULT 0x6328U |
| #define ROGUE_CR_POWER_ESTIMATE_RESULT_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_SHIFT 0U |
| #define ROGUE_CR_POWER_ESTIMATE_RESULT_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TA_PERF */ |
| #define ROGUE_CR_TA_PERF 0x7600U |
| #define ROGUE_CR_TA_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_TA_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_TA_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_TA_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_TA_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_TA_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_TA_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_TA_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_TA_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_TA_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_TA_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_TA_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_TA_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_TA_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_TA_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TA_PERF_SELECT0 */ |
| #define ROGUE_CR_TA_PERF_SELECT0 0x7608U |
| #define ROGUE_CR_TA_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TA_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_TA_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TA_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TA_PERF_SELECT1 */ |
| #define ROGUE_CR_TA_PERF_SELECT1 0x7610U |
| #define ROGUE_CR_TA_PERF_SELECT1_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TA_PERF_SELECT1_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT1_MODE_SHIFT 21U |
| #define ROGUE_CR_TA_PERF_SELECT1_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT1_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TA_PERF_SELECT1_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_SELECT1_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TA_PERF_SELECT2 */ |
| #define ROGUE_CR_TA_PERF_SELECT2 0x7618U |
| #define ROGUE_CR_TA_PERF_SELECT2_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TA_PERF_SELECT2_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT2_MODE_SHIFT 21U |
| #define ROGUE_CR_TA_PERF_SELECT2_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT2_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TA_PERF_SELECT2_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_SELECT2_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TA_PERF_SELECT3 */ |
| #define ROGUE_CR_TA_PERF_SELECT3 0x7620U |
| #define ROGUE_CR_TA_PERF_SELECT3_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TA_PERF_SELECT3_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT3_MODE_SHIFT 21U |
| #define ROGUE_CR_TA_PERF_SELECT3_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT3_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TA_PERF_SELECT3_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_SELECT3_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TA_PERF_SELECTED_BITS */ |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS 0x7648U |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_SHIFT 48U |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG3_CLRMSK 0x0000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_SHIFT 32U |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG2_CLRMSK 0xFFFF0000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_SHIFT 16U |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG1_CLRMSK 0xFFFFFFFF0000FFFFULL |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_SELECTED_BITS_REG0_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TA_PERF_COUNTER_0 */ |
| #define ROGUE_CR_TA_PERF_COUNTER_0 0x7650U |
| #define ROGUE_CR_TA_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TA_PERF_COUNTER_1 */ |
| #define ROGUE_CR_TA_PERF_COUNTER_1 0x7658U |
| #define ROGUE_CR_TA_PERF_COUNTER_1_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_COUNTER_1_REG_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_COUNTER_1_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TA_PERF_COUNTER_2 */ |
| #define ROGUE_CR_TA_PERF_COUNTER_2 0x7660U |
| #define ROGUE_CR_TA_PERF_COUNTER_2_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_COUNTER_2_REG_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_COUNTER_2_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TA_PERF_COUNTER_3 */ |
| #define ROGUE_CR_TA_PERF_COUNTER_3 0x7668U |
| #define ROGUE_CR_TA_PERF_COUNTER_3_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TA_PERF_COUNTER_3_REG_SHIFT 0U |
| #define ROGUE_CR_TA_PERF_COUNTER_3_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_RASTERISATION_PERF */ |
| #define ROGUE_CR_RASTERISATION_PERF 0x7700U |
| #define ROGUE_CR_RASTERISATION_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_RASTERISATION_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_RASTERISATION_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_RASTERISATION_PERF_SELECT0 */ |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0 0x7708U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_RASTERISATION_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_RASTERISATION_PERF_COUNTER_0 */ |
| #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0 0x7750U |
| #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_RASTERISATION_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF */ |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF 0x7800U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 */ |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0 0x7808U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 */ |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0 0x7850U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TPU_MCU_L0_PERF */ |
| #define ROGUE_CR_TPU_MCU_L0_PERF 0x7900U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_TPU_MCU_L0_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 */ |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0 0x7908U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 */ |
| #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0 0x7950U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_TPU_MCU_L0_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_USC_PERF */ |
| #define ROGUE_CR_USC_PERF 0x8100U |
| #define ROGUE_CR_USC_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_USC_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_USC_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_USC_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_USC_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_USC_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_USC_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_USC_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_USC_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_USC_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_USC_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_USC_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_USC_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_USC_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_USC_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_USC_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_USC_PERF_SELECT0 */ |
| #define ROGUE_CR_USC_PERF_SELECT0 0x8108U |
| #define ROGUE_CR_USC_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_USC_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_USC_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_USC_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_USC_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_USC_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_USC_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_USC_PERF_COUNTER_0 */ |
| #define ROGUE_CR_USC_PERF_COUNTER_0 0x8150U |
| #define ROGUE_CR_USC_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_USC_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_USC_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_JONES_IDLE */ |
| #define ROGUE_CR_JONES_IDLE 0x8328U |
| #define ROGUE_CR_JONES_IDLE_MASKFULL 0x0000000000007FFFULL |
| #define ROGUE_CR_JONES_IDLE_TDM_SHIFT 14U |
| #define ROGUE_CR_JONES_IDLE_TDM_CLRMSK 0xFFFFBFFFU |
| #define ROGUE_CR_JONES_IDLE_TDM_EN 0x00004000U |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_SHIFT 13U |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_CLRMSK 0xFFFFDFFFU |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_TLA_EN 0x00002000U |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_SHIFT 12U |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_CLRMSK 0xFFFFEFFFU |
| #define ROGUE_CR_JONES_IDLE_FB_CDC_EN 0x00001000U |
| #define ROGUE_CR_JONES_IDLE_MMU_SHIFT 11U |
| #define ROGUE_CR_JONES_IDLE_MMU_CLRMSK 0xFFFFF7FFU |
| #define ROGUE_CR_JONES_IDLE_MMU_EN 0x00000800U |
| #define ROGUE_CR_JONES_IDLE_TLA_SHIFT 10U |
| #define ROGUE_CR_JONES_IDLE_TLA_CLRMSK 0xFFFFFBFFU |
| #define ROGUE_CR_JONES_IDLE_TLA_EN 0x00000400U |
| #define ROGUE_CR_JONES_IDLE_GARTEN_SHIFT 9U |
| #define ROGUE_CR_JONES_IDLE_GARTEN_CLRMSK 0xFFFFFDFFU |
| #define ROGUE_CR_JONES_IDLE_GARTEN_EN 0x00000200U |
| #define ROGUE_CR_JONES_IDLE_HOSTIF_SHIFT 8U |
| #define ROGUE_CR_JONES_IDLE_HOSTIF_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_JONES_IDLE_HOSTIF_EN 0x00000100U |
| #define ROGUE_CR_JONES_IDLE_SOCIF_SHIFT 7U |
| #define ROGUE_CR_JONES_IDLE_SOCIF_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_JONES_IDLE_SOCIF_EN 0x00000080U |
| #define ROGUE_CR_JONES_IDLE_TILING_SHIFT 6U |
| #define ROGUE_CR_JONES_IDLE_TILING_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_JONES_IDLE_TILING_EN 0x00000040U |
| #define ROGUE_CR_JONES_IDLE_IPP_SHIFT 5U |
| #define ROGUE_CR_JONES_IDLE_IPP_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_JONES_IDLE_IPP_EN 0x00000020U |
| #define ROGUE_CR_JONES_IDLE_USCS_SHIFT 4U |
| #define ROGUE_CR_JONES_IDLE_USCS_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_JONES_IDLE_USCS_EN 0x00000010U |
| #define ROGUE_CR_JONES_IDLE_PM_SHIFT 3U |
| #define ROGUE_CR_JONES_IDLE_PM_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_JONES_IDLE_PM_EN 0x00000008U |
| #define ROGUE_CR_JONES_IDLE_CDM_SHIFT 2U |
| #define ROGUE_CR_JONES_IDLE_CDM_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_JONES_IDLE_CDM_EN 0x00000004U |
| #define ROGUE_CR_JONES_IDLE_VDM_SHIFT 1U |
| #define ROGUE_CR_JONES_IDLE_VDM_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_JONES_IDLE_VDM_EN 0x00000002U |
| #define ROGUE_CR_JONES_IDLE_BIF_SHIFT 0U |
| #define ROGUE_CR_JONES_IDLE_BIF_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_JONES_IDLE_BIF_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TORNADO_PERF */ |
| #define ROGUE_CR_TORNADO_PERF 0x8228U |
| #define ROGUE_CR_TORNADO_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_TORNADO_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_TORNADO_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_TORNADO_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_TORNADO_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_TORNADO_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_TORNADO_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_TORNADO_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_TORNADO_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_TORNADO_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_TORNADO_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_TORNADO_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_TORNADO_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_TORNADO_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TORNADO_PERF_SELECT0 */ |
| #define ROGUE_CR_TORNADO_PERF_SELECT0 0x8230U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TORNADO_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TORNADO_PERF_COUNTER_0 */ |
| #define ROGUE_CR_TORNADO_PERF_COUNTER_0 0x8268U |
| #define ROGUE_CR_TORNADO_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_TORNADO_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_TEXAS_PERF */ |
| #define ROGUE_CR_TEXAS_PERF 0x8290U |
| #define ROGUE_CR_TEXAS_PERF_MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_TEXAS_PERF_CLR_5_SHIFT 6U |
| #define ROGUE_CR_TEXAS_PERF_CLR_5_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_TEXAS_PERF_CLR_5_EN 0x00000040U |
| #define ROGUE_CR_TEXAS_PERF_CLR_4_SHIFT 5U |
| #define ROGUE_CR_TEXAS_PERF_CLR_4_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_TEXAS_PERF_CLR_4_EN 0x00000020U |
| #define ROGUE_CR_TEXAS_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_TEXAS_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_TEXAS_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_TEXAS_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_TEXAS_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_TEXAS_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_TEXAS_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_TEXAS_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_TEXAS_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_TEXAS_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_TEXAS_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_TEXAS_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_TEXAS_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_TEXAS_PERF_SELECT0 */ |
| #define ROGUE_CR_TEXAS_PERF_SELECT0 0x8298U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_SHIFT 31U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_MODE_EN 0x0000000080000000ULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_TEXAS_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_TEXAS_PERF_COUNTER_0 */ |
| #define ROGUE_CR_TEXAS_PERF_COUNTER_0 0x82D8U |
| #define ROGUE_CR_TEXAS_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_TEXAS_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_JONES_PERF */ |
| #define ROGUE_CR_JONES_PERF 0x8330U |
| #define ROGUE_CR_JONES_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_JONES_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_JONES_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_JONES_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_JONES_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_JONES_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_JONES_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_JONES_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_JONES_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_JONES_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_JONES_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_JONES_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_JONES_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_JONES_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_JONES_PERF_SELECT0 */ |
| #define ROGUE_CR_JONES_PERF_SELECT0 0x8338U |
| #define ROGUE_CR_JONES_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_JONES_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_JONES_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_JONES_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_JONES_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_JONES_PERF_COUNTER_0 */ |
| #define ROGUE_CR_JONES_PERF_COUNTER_0 0x8368U |
| #define ROGUE_CR_JONES_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_JONES_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_JONES_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_BLACKPEARL_PERF */ |
| #define ROGUE_CR_BLACKPEARL_PERF 0x8400U |
| #define ROGUE_CR_BLACKPEARL_PERF_MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_SHIFT 6U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_5_EN 0x00000040U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_SHIFT 5U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_4_EN 0x00000020U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BLACKPEARL_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BLACKPEARL_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_BLACKPEARL_PERF_SELECT0 */ |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0 0x8408U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MASKFULL 0x3FFF3FFF803FFFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_SHIFT 31U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_MODE_EN 0x0000000080000000ULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFC0FFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_BLACKPEARL_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 */ |
| #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0 0x8448U |
| #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_BLACKPEARL_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_PBE_PERF */ |
| #define ROGUE_CR_PBE_PERF 0x8478U |
| #define ROGUE_CR_PBE_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_PBE_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_PBE_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_PBE_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_PBE_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_PBE_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_PBE_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_PBE_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_PBE_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_PBE_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_PBE_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_PBE_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_PBE_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_PBE_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_PBE_PERF_SELECT0 */ |
| #define ROGUE_CR_PBE_PERF_SELECT0 0x8480U |
| #define ROGUE_CR_PBE_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_PBE_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_PBE_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_PBE_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_PBE_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_PBE_PERF_COUNTER_0 */ |
| #define ROGUE_CR_PBE_PERF_COUNTER_0 0x84B0U |
| #define ROGUE_CR_PBE_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_PBE_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_PBE_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_OCP_REVINFO */ |
| #define ROGUE_CR_OCP_REVINFO 0x9000U |
| #define ROGUE_CR_OCP_REVINFO_MASKFULL 0x00000007FFFFFFFFULL |
| #define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_SHIFT 33U |
| #define ROGUE_CR_OCP_REVINFO_HWINFO_SYSBUS_CLRMSK 0xFFFFFFF9FFFFFFFFULL |
| #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_SHIFT 32U |
| #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_OCP_REVINFO_HWINFO_MEMBUS_EN 0x0000000100000000ULL |
| #define ROGUE_CR_OCP_REVINFO_REVISION_SHIFT 0U |
| #define ROGUE_CR_OCP_REVINFO_REVISION_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_OCP_SYSCONFIG */ |
| #define ROGUE_CR_OCP_SYSCONFIG 0x9010U |
| #define ROGUE_CR_OCP_SYSCONFIG_MASKFULL 0x0000000000000FFFULL |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_SHIFT 10U |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST2_STANDBY_MODE_CLRMSK 0xFFFFF3FFU |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_SHIFT 8U |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST1_STANDBY_MODE_CLRMSK 0xFFFFFCFFU |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_SHIFT 6U |
| #define ROGUE_CR_OCP_SYSCONFIG_DUST0_STANDBY_MODE_CLRMSK 0xFFFFFF3FU |
| #define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_SHIFT 4U |
| #define ROGUE_CR_OCP_SYSCONFIG_RASCAL_STANDBYMODE_CLRMSK 0xFFFFFFCFU |
| #define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 2U |
| #define ROGUE_CR_OCP_SYSCONFIG_STANDBY_MODE_CLRMSK 0xFFFFFFF3U |
| #define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 0U |
| #define ROGUE_CR_OCP_SYSCONFIG_IDLE_MODE_CLRMSK 0xFFFFFFFCU |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_0 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_0 0x9020U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_0_INIT_MINTERRUPT_RAW_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_1 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_1 0x9028U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_1_TARGET_SINTERRUPT_RAW_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_RAW_2 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_2 0x9030U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_RAW_2_RGX_IRQ_RAW_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_0 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_0 0x9038U |
| #define ROGUE_CR_OCP_IRQSTATUS_0_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_0_INIT_MINTERRUPT_STATUS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_1 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_1 0x9040U |
| #define ROGUE_CR_OCP_IRQSTATUS_1_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_1_TARGET_SINTERRUPT_STATUS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQSTATUS_2 */ |
| #define ROGUE_CR_OCP_IRQSTATUS_2 0x9048U |
| #define ROGUE_CR_OCP_IRQSTATUS_2_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQSTATUS_2_RGX_IRQ_STATUS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_SET_0 */ |
| #define ROGUE_CR_OCP_IRQENABLE_SET_0 0x9050U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_0_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_SET_0_INIT_MINTERRUPT_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_SET_1 */ |
| #define ROGUE_CR_OCP_IRQENABLE_SET_1 0x9058U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_1_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_SET_1_TARGET_SINTERRUPT_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_SET_2 */ |
| #define ROGUE_CR_OCP_IRQENABLE_SET_2 0x9060U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_2_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_SET_2_RGX_IRQ_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_CLR_0 */ |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_0 0x9068U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_0_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_0_INIT_MINTERRUPT_DISABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_CLR_1 */ |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_1 0x9070U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_1_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_1_TARGET_SINTERRUPT_DISABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQENABLE_CLR_2 */ |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_2 0x9078U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_2_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_IRQENABLE_CLR_2_RGX_IRQ_DISABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_IRQ_EVENT */ |
| #define ROGUE_CR_OCP_IRQ_EVENT 0x9080U |
| #define ROGUE_CR_OCP_IRQ_EVENT_MASKFULL 0x00000000000FFFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_SHIFT 19U |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFF7FFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNEXPECTED_RDATA_EN 0x0000000000080000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_SHIFT 18U |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFBFFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETH_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000040000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_SHIFT 17U |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_CLRMSK 0xFFFFFFFFFFFDFFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNEXPECTED_RDATA_EN 0x0000000000020000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_SHIFT 16U |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_CLRMSK 0xFFFFFFFFFFFEFFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_TARGETS_RCVD_UNSUPPORTED_MCMD_EN 0x0000000000010000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_SHIFT 15U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFF7FFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000008000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_SHIFT 14U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFBFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_RESP_ERR_FAIL_EN 0x0000000000004000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_SHIFT 13U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFDFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RCVD_UNUSED_TAGID_EN 0x0000000000002000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_SHIFT 12U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFEFFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT3_RDATA_FIFO_OVERFILL_EN 0x0000000000001000ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_SHIFT 11U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFF7FFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000800ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_SHIFT 10U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_RESP_ERR_FAIL_EN 0x0000000000000400ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_SHIFT 9U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFDFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RCVD_UNUSED_TAGID_EN 0x0000000000000200ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_SHIFT 8U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFEFFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT2_RDATA_FIFO_OVERFILL_EN 0x0000000000000100ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_SHIFT 7U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFF7FULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000080ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_SHIFT 6U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFBFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_RESP_ERR_FAIL_EN 0x0000000000000040ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_SHIFT 5U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RCVD_UNUSED_TAGID_EN 0x0000000000000020ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_SHIFT 4U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT1_RDATA_FIFO_OVERFILL_EN 0x0000000000000010ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_SHIFT 3U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_IMG_PAGE_BOUNDARY_CROSS_EN 0x0000000000000008ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_SHIFT 2U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_RESP_ERR_FAIL_EN 0x0000000000000004ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_SHIFT 1U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_CLRMSK 0xFFFFFFFFFFFFFFFDULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RCVD_UNUSED_TAGID_EN 0x0000000000000002ULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_SHIFT 0U |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_OCP_IRQ_EVENT_INIT0_RDATA_FIFO_OVERFILL_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_OCP_DEBUG_CONFIG */ |
| #define ROGUE_CR_OCP_DEBUG_CONFIG 0x9088U |
| #define ROGUE_CR_OCP_DEBUG_CONFIG_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_SHIFT 0U |
| #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_OCP_DEBUG_CONFIG_REG_EN 0x00000001U |
| |
| /* Register ROGUE_CR_OCP_DEBUG_STATUS */ |
| #define ROGUE_CR_OCP_DEBUG_STATUS 0x9090U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_MASKFULL 0x001F1F77FFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_SHIFT 51U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SDISCACK_CLRMSK 0xFFE7FFFFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_SHIFT 50U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_CLRMSK 0xFFFBFFFFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SCONNECT_EN 0x0004000000000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_SHIFT 48U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_MCONNECT_CLRMSK 0xFFFCFFFFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_SHIFT 43U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SDISCACK_CLRMSK 0xFFFFE7FFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_SHIFT 42U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_CLRMSK 0xFFFFFBFFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SCONNECT_EN 0x0000040000000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_SHIFT 40U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_MCONNECT_CLRMSK 0xFFFFFCFFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_SHIFT 38U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_CLRMSK 0xFFFFFFBFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_BUSY_EN 0x0000004000000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_SHIFT 37U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_CLRMSK 0xFFFFFFDFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_CMD_FIFO_FULL_EN 0x0000002000000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_SHIFT 36U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_CLRMSK 0xFFFFFFEFFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETH_SRESP_ERROR_EN 0x0000001000000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_SHIFT 34U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_CLRMSK 0xFFFFFFFBFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_BUSY_EN 0x0000000400000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_SHIFT 33U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_CLRMSK 0xFFFFFFFDFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_CMD_FIFO_FULL_EN 0x0000000200000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_SHIFT 32U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_CLRMSK 0xFFFFFFFEFFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_TARGETS_SRESP_ERROR_EN 0x0000000100000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_SHIFT 31U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_CLRMSK 0xFFFFFFFF7FFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_RESERVED_EN 0x0000000080000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_SHIFT 30U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_CLRMSK 0xFFFFFFFFBFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SWAIT_EN 0x0000000040000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_SHIFT 29U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_CLRMSK 0xFFFFFFFFDFFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCREQ_EN 0x0000000020000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_SHIFT 27U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MDISCACK_CLRMSK 0xFFFFFFFFE7FFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_SHIFT 26U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_CLRMSK 0xFFFFFFFFFBFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_SCONNECT_EN 0x0000000004000000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_SHIFT 24U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT3_MCONNECT_CLRMSK 0xFFFFFFFFFCFFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_SHIFT 23U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_CLRMSK 0xFFFFFFFFFF7FFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_RESERVED_EN 0x0000000000800000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_SHIFT 22U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_CLRMSK 0xFFFFFFFFFFBFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SWAIT_EN 0x0000000000400000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_SHIFT 21U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCREQ_EN 0x0000000000200000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_SHIFT 19U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MDISCACK_CLRMSK 0xFFFFFFFFFFE7FFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_SHIFT 18U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_CLRMSK 0xFFFFFFFFFFFBFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_SCONNECT_EN 0x0000000000040000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_SHIFT 16U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT2_MCONNECT_CLRMSK 0xFFFFFFFFFFFCFFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_SHIFT 15U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_CLRMSK 0xFFFFFFFFFFFF7FFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_RESERVED_EN 0x0000000000008000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_SHIFT 14U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_CLRMSK 0xFFFFFFFFFFFFBFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SWAIT_EN 0x0000000000004000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_SHIFT 13U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFDFFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCREQ_EN 0x0000000000002000ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_SHIFT 11U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MDISCACK_CLRMSK 0xFFFFFFFFFFFFE7FFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_SHIFT 10U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFBFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_SCONNECT_EN 0x0000000000000400ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_SHIFT 8U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT1_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFCFFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_SHIFT 7U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_CLRMSK 0xFFFFFFFFFFFFFF7FULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_RESERVED_EN 0x0000000000000080ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_SHIFT 6U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_CLRMSK 0xFFFFFFFFFFFFFFBFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SWAIT_EN 0x0000000000000040ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_SHIFT 5U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_CLRMSK 0xFFFFFFFFFFFFFFDFULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCREQ_EN 0x0000000000000020ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_SHIFT 3U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MDISCACK_CLRMSK 0xFFFFFFFFFFFFFFE7ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_SHIFT 2U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_SCONNECT_EN 0x0000000000000004ULL |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_SHIFT 0U |
| #define ROGUE_CR_OCP_DEBUG_STATUS_INIT0_MCONNECT_CLRMSK 0xFFFFFFFFFFFFFFFCULL |
| |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_SHIFT 6U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PM_ALIST_EN 0x00000040U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_SHIFT 5U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_HOST_EN 0x00000020U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_SHIFT 4U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_META_EN 0x00000010U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_SHIFT 3U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_ZLS_EN 0x00000008U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_SHIFT 2U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_TE_EN 0x00000004U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_SHIFT 1U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_PB_VCE_EN 0x00000002U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_SHIFT 0U |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_TRUST_DM_TYPE_TLA_EN 0x00000001U |
| |
| #define ROGUE_CR_BIF_TRUST_DM_MASK 0x0000007FU |
| |
| /* Register ROGUE_CR_BIF_TRUST */ |
| #define ROGUE_CR_BIF_TRUST 0xA000U |
| #define ROGUE_CR_BIF_TRUST_MASKFULL 0x00000000001FFFFFULL |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_SHIFT 20U |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFEFFFFFU |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_VERTEX_DM_TRUSTED_EN 0x00100000U |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_SHIFT 19U |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_CLRMSK 0xFFF7FFFFU |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_VERTEX_DM_TRUSTED_EN 0x00080000U |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_SHIFT 18U |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_CLRMSK 0xFFFBFFFFU |
| #define ROGUE_CR_BIF_TRUST_OTHER_RAY_DM_TRUSTED_EN 0x00040000U |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_SHIFT 17U |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_CLRMSK 0xFFFDFFFFU |
| #define ROGUE_CR_BIF_TRUST_MCU_RAY_DM_TRUSTED_EN 0x00020000U |
| #define ROGUE_CR_BIF_TRUST_ENABLE_SHIFT 16U |
| #define ROGUE_CR_BIF_TRUST_ENABLE_CLRMSK 0xFFFEFFFFU |
| #define ROGUE_CR_BIF_TRUST_ENABLE_EN 0x00010000U |
| #define ROGUE_CR_BIF_TRUST_DM_TRUSTED_SHIFT 9U |
| #define ROGUE_CR_BIF_TRUST_DM_TRUSTED_CLRMSK 0xFFFF01FFU |
| #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_SHIFT 8U |
| #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_BIF_TRUST_OTHER_COMPUTE_DM_TRUSTED_EN 0x00000100U |
| #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_SHIFT 7U |
| #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFF7FU |
| #define ROGUE_CR_BIF_TRUST_MCU_COMPUTE_DM_TRUSTED_EN 0x00000080U |
| #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_SHIFT 6U |
| #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_BIF_TRUST_PBE_COMPUTE_DM_TRUSTED_EN 0x00000040U |
| #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_SHIFT 5U |
| #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_BIF_TRUST_OTHER_PIXEL_DM_TRUSTED_EN 0x00000020U |
| #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_SHIFT 4U |
| #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_BIF_TRUST_MCU_PIXEL_DM_TRUSTED_EN 0x00000010U |
| #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_SHIFT 3U |
| #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_BIF_TRUST_PBE_PIXEL_DM_TRUSTED_EN 0x00000008U |
| #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_SHIFT 2U |
| #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_BIF_TRUST_OTHER_VERTEX_DM_TRUSTED_EN 0x00000004U |
| #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_SHIFT 1U |
| #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_BIF_TRUST_MCU_VERTEX_DM_TRUSTED_EN 0x00000002U |
| #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_SHIFT 0U |
| #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_BIF_TRUST_PBE_VERTEX_DM_TRUSTED_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SYS_BUS_SECURE */ |
| #define ROGUE_CR_SYS_BUS_SECURE 0xA100U |
| #define ROGUE_CR_SYS_BUS_SECURE__SECR__MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_SYS_BUS_SECURE_MASKFULL 0x0000000000000001ULL |
| #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_SHIFT 0U |
| #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SYS_BUS_SECURE_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_FBA_FC0_CHECKSUM */ |
| #define ROGUE_CR_FBA_FC0_CHECKSUM 0xD170U |
| #define ROGUE_CR_FBA_FC0_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_FBA_FC0_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_FBA_FC1_CHECKSUM */ |
| #define ROGUE_CR_FBA_FC1_CHECKSUM 0xD178U |
| #define ROGUE_CR_FBA_FC1_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_FBA_FC1_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_FBA_FC2_CHECKSUM */ |
| #define ROGUE_CR_FBA_FC2_CHECKSUM 0xD180U |
| #define ROGUE_CR_FBA_FC2_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_FBA_FC2_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_FBA_FC3_CHECKSUM */ |
| #define ROGUE_CR_FBA_FC3_CHECKSUM 0xD188U |
| #define ROGUE_CR_FBA_FC3_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_FBA_FC3_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_CLK_CTRL2 */ |
| #define ROGUE_CR_CLK_CTRL2 0xD200U |
| #define ROGUE_CR_CLK_CTRL2_MASKFULL 0x0000000000000F33ULL |
| #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_SHIFT 10U |
| #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_CLRMSK 0xFFFFFFFFFFFFF3FFULL |
| #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_ON 0x0000000000000400ULL |
| #define ROGUE_CR_CLK_CTRL2_MCU_FBTC_AUTO 0x0000000000000800ULL |
| #define ROGUE_CR_CLK_CTRL2_VRDM_SHIFT 8U |
| #define ROGUE_CR_CLK_CTRL2_VRDM_CLRMSK 0xFFFFFFFFFFFFFCFFULL |
| #define ROGUE_CR_CLK_CTRL2_VRDM_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL2_VRDM_ON 0x0000000000000100ULL |
| #define ROGUE_CR_CLK_CTRL2_VRDM_AUTO 0x0000000000000200ULL |
| #define ROGUE_CR_CLK_CTRL2_SH_SHIFT 4U |
| #define ROGUE_CR_CLK_CTRL2_SH_CLRMSK 0xFFFFFFFFFFFFFFCFULL |
| #define ROGUE_CR_CLK_CTRL2_SH_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL2_SH_ON 0x0000000000000010ULL |
| #define ROGUE_CR_CLK_CTRL2_SH_AUTO 0x0000000000000020ULL |
| #define ROGUE_CR_CLK_CTRL2_FBA_SHIFT 0U |
| #define ROGUE_CR_CLK_CTRL2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFCULL |
| #define ROGUE_CR_CLK_CTRL2_FBA_OFF 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_CTRL2_FBA_ON 0x0000000000000001ULL |
| #define ROGUE_CR_CLK_CTRL2_FBA_AUTO 0x0000000000000002ULL |
| |
| /* Register ROGUE_CR_CLK_STATUS2 */ |
| #define ROGUE_CR_CLK_STATUS2 0xD208U |
| #define ROGUE_CR_CLK_STATUS2_MASKFULL 0x0000000000000015ULL |
| #define ROGUE_CR_CLK_STATUS2_VRDM_SHIFT 4U |
| #define ROGUE_CR_CLK_STATUS2_VRDM_CLRMSK 0xFFFFFFFFFFFFFFEFULL |
| #define ROGUE_CR_CLK_STATUS2_VRDM_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS2_VRDM_RUNNING 0x0000000000000010ULL |
| #define ROGUE_CR_CLK_STATUS2_SH_SHIFT 2U |
| #define ROGUE_CR_CLK_STATUS2_SH_CLRMSK 0xFFFFFFFFFFFFFFFBULL |
| #define ROGUE_CR_CLK_STATUS2_SH_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS2_SH_RUNNING 0x0000000000000004ULL |
| #define ROGUE_CR_CLK_STATUS2_FBA_SHIFT 0U |
| #define ROGUE_CR_CLK_STATUS2_FBA_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_CLK_STATUS2_FBA_GATED 0x0000000000000000ULL |
| #define ROGUE_CR_CLK_STATUS2_FBA_RUNNING 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_RPM_SHF_FPL */ |
| #define ROGUE_CR_RPM_SHF_FPL 0xD520U |
| #define ROGUE_CR_RPM_SHF_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL |
| #define ROGUE_CR_RPM_SHF_FPL_SIZE_SHIFT 40U |
| #define ROGUE_CR_RPM_SHF_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL |
| #define ROGUE_CR_RPM_SHF_FPL_BASE_SHIFT 2U |
| #define ROGUE_CR_RPM_SHF_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL |
| #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSHIFT 2U |
| #define ROGUE_CR_RPM_SHF_FPL_BASE_ALIGNSIZE 4U |
| |
| /* Register ROGUE_CR_RPM_SHF_FPL_READ */ |
| #define ROGUE_CR_RPM_SHF_FPL_READ 0xD528U |
| #define ROGUE_CR_RPM_SHF_FPL_READ_MASKFULL 0x00000000007FFFFFULL |
| #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_SHIFT 22U |
| #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU |
| #define ROGUE_CR_RPM_SHF_FPL_READ_TOGGLE_EN 0x00400000U |
| #define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_SHIFT 0U |
| #define ROGUE_CR_RPM_SHF_FPL_READ_OFFSET_CLRMSK 0xFFC00000U |
| |
| /* Register ROGUE_CR_RPM_SHF_FPL_WRITE */ |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE 0xD530U |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_SHIFT 22U |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_TOGGLE_EN 0x00400000U |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_SHIFT 0U |
| #define ROGUE_CR_RPM_SHF_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U |
| |
| /* Register ROGUE_CR_RPM_SHG_FPL */ |
| #define ROGUE_CR_RPM_SHG_FPL 0xD538U |
| #define ROGUE_CR_RPM_SHG_FPL_MASKFULL 0x3FFFFFFFFFFFFFFCULL |
| #define ROGUE_CR_RPM_SHG_FPL_SIZE_SHIFT 40U |
| #define ROGUE_CR_RPM_SHG_FPL_SIZE_CLRMSK 0xC00000FFFFFFFFFFULL |
| #define ROGUE_CR_RPM_SHG_FPL_BASE_SHIFT 2U |
| #define ROGUE_CR_RPM_SHG_FPL_BASE_CLRMSK 0xFFFFFF0000000003ULL |
| #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSHIFT 2U |
| #define ROGUE_CR_RPM_SHG_FPL_BASE_ALIGNSIZE 4U |
| |
| /* Register ROGUE_CR_RPM_SHG_FPL_READ */ |
| #define ROGUE_CR_RPM_SHG_FPL_READ 0xD540U |
| #define ROGUE_CR_RPM_SHG_FPL_READ_MASKFULL 0x00000000007FFFFFULL |
| #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_SHIFT 22U |
| #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_CLRMSK 0xFFBFFFFFU |
| #define ROGUE_CR_RPM_SHG_FPL_READ_TOGGLE_EN 0x00400000U |
| #define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_SHIFT 0U |
| #define ROGUE_CR_RPM_SHG_FPL_READ_OFFSET_CLRMSK 0xFFC00000U |
| |
| /* Register ROGUE_CR_RPM_SHG_FPL_WRITE */ |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE 0xD548U |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_MASKFULL 0x00000000007FFFFFULL |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_SHIFT 22U |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_CLRMSK 0xFFBFFFFFU |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_TOGGLE_EN 0x00400000U |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_SHIFT 0U |
| #define ROGUE_CR_RPM_SHG_FPL_WRITE_OFFSET_CLRMSK 0xFFC00000U |
| |
| /* Register ROGUE_CR_SH_PERF */ |
| #define ROGUE_CR_SH_PERF 0xD5F8U |
| #define ROGUE_CR_SH_PERF_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_SH_PERF_CLR_3_SHIFT 4U |
| #define ROGUE_CR_SH_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SH_PERF_CLR_3_EN 0x00000010U |
| #define ROGUE_CR_SH_PERF_CLR_2_SHIFT 3U |
| #define ROGUE_CR_SH_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SH_PERF_CLR_2_EN 0x00000008U |
| #define ROGUE_CR_SH_PERF_CLR_1_SHIFT 2U |
| #define ROGUE_CR_SH_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SH_PERF_CLR_1_EN 0x00000004U |
| #define ROGUE_CR_SH_PERF_CLR_0_SHIFT 1U |
| #define ROGUE_CR_SH_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SH_PERF_CLR_0_EN 0x00000002U |
| #define ROGUE_CR_SH_PERF_CTRL_ENABLE_SHIFT 0U |
| #define ROGUE_CR_SH_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SH_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SH_PERF_SELECT0 */ |
| #define ROGUE_CR_SH_PERF_SELECT0 0xD600U |
| #define ROGUE_CR_SH_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define ROGUE_CR_SH_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define ROGUE_CR_SH_PERF_SELECT0_MODE_SHIFT 21U |
| #define ROGUE_CR_SH_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define ROGUE_CR_SH_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define ROGUE_CR_SH_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define ROGUE_CR_SH_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_SH_PERF_COUNTER_0 */ |
| #define ROGUE_CR_SH_PERF_COUNTER_0 0xD628U |
| #define ROGUE_CR_SH_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SH_PERF_COUNTER_0_REG_SHIFT 0U |
| #define ROGUE_CR_SH_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SHF_SHG_CHECKSUM */ |
| #define ROGUE_CR_SHF_SHG_CHECKSUM 0xD1C0U |
| #define ROGUE_CR_SHF_SHG_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_SHF_SHG_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM */ |
| #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM 0xD1C8U |
| #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_SHF_VERTEX_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SHF_VARY_BIF_CHECKSUM */ |
| #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM 0xD1D0U |
| #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_SHF_VARY_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_RPM_BIF_CHECKSUM */ |
| #define ROGUE_CR_RPM_BIF_CHECKSUM 0xD1D8U |
| #define ROGUE_CR_RPM_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_RPM_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SHG_BIF_CHECKSUM */ |
| #define ROGUE_CR_SHG_BIF_CHECKSUM 0xD1E0U |
| #define ROGUE_CR_SHG_BIF_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_SHG_BIF_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register ROGUE_CR_SHG_FE_BE_CHECKSUM */ |
| #define ROGUE_CR_SHG_FE_BE_CHECKSUM 0xD1E8U |
| #define ROGUE_CR_SHG_FE_BE_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_SHIFT 0U |
| #define ROGUE_CR_SHG_FE_BE_CHECKSUM_VALUE_CLRMSK 0x00000000U |
| |
| /* Register DPX_CR_BF_PERF */ |
| #define DPX_CR_BF_PERF 0xC458U |
| #define DPX_CR_BF_PERF_MASKFULL 0x000000000000001FULL |
| #define DPX_CR_BF_PERF_CLR_3_SHIFT 4U |
| #define DPX_CR_BF_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define DPX_CR_BF_PERF_CLR_3_EN 0x00000010U |
| #define DPX_CR_BF_PERF_CLR_2_SHIFT 3U |
| #define DPX_CR_BF_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define DPX_CR_BF_PERF_CLR_2_EN 0x00000008U |
| #define DPX_CR_BF_PERF_CLR_1_SHIFT 2U |
| #define DPX_CR_BF_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_BF_PERF_CLR_1_EN 0x00000004U |
| #define DPX_CR_BF_PERF_CLR_0_SHIFT 1U |
| #define DPX_CR_BF_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define DPX_CR_BF_PERF_CLR_0_EN 0x00000002U |
| #define DPX_CR_BF_PERF_CTRL_ENABLE_SHIFT 0U |
| #define DPX_CR_BF_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_BF_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register DPX_CR_BF_PERF_SELECT0 */ |
| #define DPX_CR_BF_PERF_SELECT0 0xC460U |
| #define DPX_CR_BF_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define DPX_CR_BF_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define DPX_CR_BF_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define DPX_CR_BF_PERF_SELECT0_MODE_SHIFT 21U |
| #define DPX_CR_BF_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define DPX_CR_BF_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define DPX_CR_BF_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define DPX_CR_BF_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register DPX_CR_BF_PERF_COUNTER_0 */ |
| #define DPX_CR_BF_PERF_COUNTER_0 0xC488U |
| #define DPX_CR_BF_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_BF_PERF_COUNTER_0_REG_SHIFT 0U |
| #define DPX_CR_BF_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register DPX_CR_BT_PERF */ |
| #define DPX_CR_BT_PERF 0xC3D0U |
| #define DPX_CR_BT_PERF_MASKFULL 0x000000000000001FULL |
| #define DPX_CR_BT_PERF_CLR_3_SHIFT 4U |
| #define DPX_CR_BT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define DPX_CR_BT_PERF_CLR_3_EN 0x00000010U |
| #define DPX_CR_BT_PERF_CLR_2_SHIFT 3U |
| #define DPX_CR_BT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define DPX_CR_BT_PERF_CLR_2_EN 0x00000008U |
| #define DPX_CR_BT_PERF_CLR_1_SHIFT 2U |
| #define DPX_CR_BT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_BT_PERF_CLR_1_EN 0x00000004U |
| #define DPX_CR_BT_PERF_CLR_0_SHIFT 1U |
| #define DPX_CR_BT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define DPX_CR_BT_PERF_CLR_0_EN 0x00000002U |
| #define DPX_CR_BT_PERF_CTRL_ENABLE_SHIFT 0U |
| #define DPX_CR_BT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_BT_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register DPX_CR_BT_PERF_SELECT0 */ |
| #define DPX_CR_BT_PERF_SELECT0 0xC3D8U |
| #define DPX_CR_BT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define DPX_CR_BT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define DPX_CR_BT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define DPX_CR_BT_PERF_SELECT0_MODE_SHIFT 21U |
| #define DPX_CR_BT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define DPX_CR_BT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define DPX_CR_BT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define DPX_CR_BT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register DPX_CR_BT_PERF_COUNTER_0 */ |
| #define DPX_CR_BT_PERF_COUNTER_0 0xC420U |
| #define DPX_CR_BT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_BT_PERF_COUNTER_0_REG_SHIFT 0U |
| #define DPX_CR_BT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register DPX_CR_RQ_USC_DEBUG */ |
| #define DPX_CR_RQ_USC_DEBUG 0xC110U |
| #define DPX_CR_RQ_USC_DEBUG_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_RQ_USC_DEBUG_CHECKSUM_SHIFT 0U |
| #define DPX_CR_RQ_USC_DEBUG_CHECKSUM_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register DPX_CR_BIF_FAULT_BANK_MMU_STATUS */ |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS 0xC5C8U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_MASKFULL 0x000000000000F775ULL |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_SHIFT 12U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_CAT_BASE_CLRMSK 0xFFFF0FFFU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_SHIFT 8U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_PAGE_SIZE_CLRMSK 0xFFFFF8FFU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_SHIFT 5U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_DATA_TYPE_CLRMSK 0xFFFFFF9FU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_SHIFT 4U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_CLRMSK 0xFFFFFFEFU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_RO_EN 0x00000010U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_SHIFT 2U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_PM_META_RO_EN 0x00000004U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_SHIFT 0U |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_BIF_FAULT_BANK_MMU_STATUS_FAULT_EN 0x00000001U |
| |
| /* Register DPX_CR_BIF_FAULT_BANK_REQ_STATUS */ |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS 0xC5D0U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_MASKFULL 0x03FFFFFFFFFFFFF0ULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_SHIFT 57U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_CLRMSK 0xFDFFFFFFFFFFFFFFULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_RNW_EN 0x0200000000000000ULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_SHIFT 44U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_SB_CLRMSK 0xFE000FFFFFFFFFFFULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_SHIFT 40U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_TAG_ID_CLRMSK 0xFFFFF0FFFFFFFFFFULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_SHIFT 4U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_CLRMSK 0xFFFFFF000000000FULL |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSHIFT 4U |
| #define DPX_CR_BIF_FAULT_BANK_REQ_STATUS_ADDRESS_ALIGNSIZE 16U |
| |
| /* Register DPX_CR_BIF_MMU_STATUS */ |
| #define DPX_CR_BIF_MMU_STATUS 0xC5D8U |
| #define DPX_CR_BIF_MMU_STATUS_MASKFULL 0x000000000FFFFFF7ULL |
| #define DPX_CR_BIF_MMU_STATUS_PC_DATA_SHIFT 20U |
| #define DPX_CR_BIF_MMU_STATUS_PC_DATA_CLRMSK 0xF00FFFFFU |
| #define DPX_CR_BIF_MMU_STATUS_PD_DATA_SHIFT 12U |
| #define DPX_CR_BIF_MMU_STATUS_PD_DATA_CLRMSK 0xFFF00FFFU |
| #define DPX_CR_BIF_MMU_STATUS_PT_DATA_SHIFT 4U |
| #define DPX_CR_BIF_MMU_STATUS_PT_DATA_CLRMSK 0xFFFFF00FU |
| #define DPX_CR_BIF_MMU_STATUS_STALLED_SHIFT 2U |
| #define DPX_CR_BIF_MMU_STATUS_STALLED_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_BIF_MMU_STATUS_STALLED_EN 0x00000004U |
| #define DPX_CR_BIF_MMU_STATUS_PAUSED_SHIFT 1U |
| #define DPX_CR_BIF_MMU_STATUS_PAUSED_CLRMSK 0xFFFFFFFDU |
| #define DPX_CR_BIF_MMU_STATUS_PAUSED_EN 0x00000002U |
| #define DPX_CR_BIF_MMU_STATUS_BUSY_SHIFT 0U |
| #define DPX_CR_BIF_MMU_STATUS_BUSY_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U |
| |
| /* Register DPX_CR_RT_PERF */ |
| #define DPX_CR_RT_PERF 0xC700U |
| #define DPX_CR_RT_PERF_MASKFULL 0x000000000000001FULL |
| #define DPX_CR_RT_PERF_CLR_3_SHIFT 4U |
| #define DPX_CR_RT_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define DPX_CR_RT_PERF_CLR_3_EN 0x00000010U |
| #define DPX_CR_RT_PERF_CLR_2_SHIFT 3U |
| #define DPX_CR_RT_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define DPX_CR_RT_PERF_CLR_2_EN 0x00000008U |
| #define DPX_CR_RT_PERF_CLR_1_SHIFT 2U |
| #define DPX_CR_RT_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_RT_PERF_CLR_1_EN 0x00000004U |
| #define DPX_CR_RT_PERF_CLR_0_SHIFT 1U |
| #define DPX_CR_RT_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define DPX_CR_RT_PERF_CLR_0_EN 0x00000002U |
| #define DPX_CR_RT_PERF_CTRL_ENABLE_SHIFT 0U |
| #define DPX_CR_RT_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_RT_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register DPX_CR_RT_PERF_SELECT0 */ |
| #define DPX_CR_RT_PERF_SELECT0 0xC708U |
| #define DPX_CR_RT_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define DPX_CR_RT_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define DPX_CR_RT_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define DPX_CR_RT_PERF_SELECT0_MODE_SHIFT 21U |
| #define DPX_CR_RT_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define DPX_CR_RT_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define DPX_CR_RT_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define DPX_CR_RT_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register DPX_CR_RT_PERF_COUNTER_0 */ |
| #define DPX_CR_RT_PERF_COUNTER_0 0xC730U |
| #define DPX_CR_RT_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_RT_PERF_COUNTER_0_REG_SHIFT 0U |
| #define DPX_CR_RT_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register DPX_CR_BX_TU_PERF */ |
| #define DPX_CR_BX_TU_PERF 0xC908U |
| #define DPX_CR_BX_TU_PERF_MASKFULL 0x000000000000001FULL |
| #define DPX_CR_BX_TU_PERF_CLR_3_SHIFT 4U |
| #define DPX_CR_BX_TU_PERF_CLR_3_CLRMSK 0xFFFFFFEFU |
| #define DPX_CR_BX_TU_PERF_CLR_3_EN 0x00000010U |
| #define DPX_CR_BX_TU_PERF_CLR_2_SHIFT 3U |
| #define DPX_CR_BX_TU_PERF_CLR_2_CLRMSK 0xFFFFFFF7U |
| #define DPX_CR_BX_TU_PERF_CLR_2_EN 0x00000008U |
| #define DPX_CR_BX_TU_PERF_CLR_1_SHIFT 2U |
| #define DPX_CR_BX_TU_PERF_CLR_1_CLRMSK 0xFFFFFFFBU |
| #define DPX_CR_BX_TU_PERF_CLR_1_EN 0x00000004U |
| #define DPX_CR_BX_TU_PERF_CLR_0_SHIFT 1U |
| #define DPX_CR_BX_TU_PERF_CLR_0_CLRMSK 0xFFFFFFFDU |
| #define DPX_CR_BX_TU_PERF_CLR_0_EN 0x00000002U |
| #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_SHIFT 0U |
| #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_CLRMSK 0xFFFFFFFEU |
| #define DPX_CR_BX_TU_PERF_CTRL_ENABLE_EN 0x00000001U |
| |
| /* Register DPX_CR_BX_TU_PERF_SELECT0 */ |
| #define DPX_CR_BX_TU_PERF_SELECT0 0xC910U |
| #define DPX_CR_BX_TU_PERF_SELECT0_MASKFULL 0x3FFF3FFF003FFFFFULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_SHIFT 48U |
| #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MAX_CLRMSK 0xC000FFFFFFFFFFFFULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_SHIFT 32U |
| #define DPX_CR_BX_TU_PERF_SELECT0_BATCH_MIN_CLRMSK 0xFFFFC000FFFFFFFFULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_MODE_SHIFT 21U |
| #define DPX_CR_BX_TU_PERF_SELECT0_MODE_CLRMSK 0xFFFFFFFFFFDFFFFFULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_MODE_EN 0x0000000000200000ULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_SHIFT 16U |
| #define DPX_CR_BX_TU_PERF_SELECT0_GROUP_SELECT_CLRMSK 0xFFFFFFFFFFE0FFFFULL |
| #define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_SHIFT 0U |
| #define DPX_CR_BX_TU_PERF_SELECT0_BIT_SELECT_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register DPX_CR_BX_TU_PERF_COUNTER_0 */ |
| #define DPX_CR_BX_TU_PERF_COUNTER_0 0xC938U |
| #define DPX_CR_BX_TU_PERF_COUNTER_0_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_BX_TU_PERF_COUNTER_0_REG_SHIFT 0U |
| #define DPX_CR_BX_TU_PERF_COUNTER_0_REG_CLRMSK 0x00000000U |
| |
| /* Register DPX_CR_RS_PDS_RR_CHECKSUM */ |
| #define DPX_CR_RS_PDS_RR_CHECKSUM 0xC0F0U |
| #define DPX_CR_RS_PDS_RR_CHECKSUM_MASKFULL 0x00000000FFFFFFFFULL |
| #define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_SHIFT 0U |
| #define DPX_CR_RS_PDS_RR_CHECKSUM_VALUE_CLRMSK 0xFFFFFFFF00000000ULL |
| |
| /* Register ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT */ |
| #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT 0xE140U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_MASKFULL 0x00000000000000FFULL |
| #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_SHIFT 0U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_CONTEXT_ID_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_MMU_CBASE_MAPPING */ |
| #define ROGUE_CR_MMU_CBASE_MAPPING 0xE148U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_MASKFULL 0x000000000FFFFFFFULL |
| #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_SHIFT 0U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_CLRMSK 0xF0000000U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSHIFT 12U |
| #define ROGUE_CR_MMU_CBASE_MAPPING_BASE_ADDR_ALIGNSIZE 4096U |
| |
| /* Register ROGUE_CR_MMU_FAULT_STATUS */ |
| #define ROGUE_CR_MMU_FAULT_STATUS 0xE150U |
| #define ROGUE_CR_MMU_FAULT_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_SHIFT 28U |
| #define ROGUE_CR_MMU_FAULT_STATUS_ADDRESS_CLRMSK 0x000000000FFFFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_SHIFT 20U |
| #define ROGUE_CR_MMU_FAULT_STATUS_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_SHIFT 12U |
| #define ROGUE_CR_MMU_FAULT_STATUS_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_SHIFT 6U |
| #define ROGUE_CR_MMU_FAULT_STATUS_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_SHIFT 4U |
| #define ROGUE_CR_MMU_FAULT_STATUS_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_RNW_SHIFT 3U |
| #define ROGUE_CR_MMU_FAULT_STATUS_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_RNW_EN 0x0000000000000008ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_TYPE_SHIFT 1U |
| #define ROGUE_CR_MMU_FAULT_STATUS_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_SHIFT 0U |
| #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_FAULT_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_MMU_FAULT_STATUS_META */ |
| #define ROGUE_CR_MMU_FAULT_STATUS_META 0xE158U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_SHIFT 28U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_ADDRESS_CLRMSK 0x000000000FFFFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_SHIFT 20U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_CONTEXT_CLRMSK 0xFFFFFFFFF00FFFFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_SHIFT 12U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_TAG_SB_CLRMSK 0xFFFFFFFFFFF00FFFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_SHIFT 6U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_REQ_ID_CLRMSK 0xFFFFFFFFFFFFF03FULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_SHIFT 4U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_LEVEL_CLRMSK 0xFFFFFFFFFFFFFFCFULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_SHIFT 3U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_CLRMSK 0xFFFFFFFFFFFFFFF7ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_RNW_EN 0x0000000000000008ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_SHIFT 1U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_TYPE_CLRMSK 0xFFFFFFFFFFFFFFF9ULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_SHIFT 0U |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_CLRMSK 0xFFFFFFFFFFFFFFFEULL |
| #define ROGUE_CR_MMU_FAULT_STATUS_META_FAULT_EN 0x0000000000000001ULL |
| |
| /* Register ROGUE_CR_SLC3_CTRL_MISC */ |
| #define ROGUE_CR_SLC3_CTRL_MISC 0xE200U |
| #define ROGUE_CR_SLC3_CTRL_MISC_MASKFULL 0x0000000000000107ULL |
| #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_SHIFT 8U |
| #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_CLRMSK 0xFFFFFEFFU |
| #define ROGUE_CR_SLC3_CTRL_MISC_WRITE_COMBINER_EN 0x00000100U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SHIFT 0U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_CLRMSK 0xFFFFFFF8U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_LINEAR 0x00000000U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_IN_PAGE_HASH 0x00000001U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_FIXED_PVR_HASH 0x00000002U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_SCRAMBLE_PVR_HASH 0x00000003U |
| #define ROGUE_CR_SLC3_CTRL_MISC_ADDR_DECODE_MODE_WEAVED_HASH 0x00000004U |
| |
| /* Register ROGUE_CR_SLC3_SCRAMBLE */ |
| #define ROGUE_CR_SLC3_SCRAMBLE 0xE208U |
| #define ROGUE_CR_SLC3_SCRAMBLE_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_SCRAMBLE_BITS_SHIFT 0U |
| #define ROGUE_CR_SLC3_SCRAMBLE_BITS_CLRMSK 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_SLC3_SCRAMBLE2 */ |
| #define ROGUE_CR_SLC3_SCRAMBLE2 0xE210U |
| #define ROGUE_CR_SLC3_SCRAMBLE2_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_SCRAMBLE2_BITS_SHIFT 0U |
| #define ROGUE_CR_SLC3_SCRAMBLE2_BITS_CLRMSK 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_SLC3_SCRAMBLE3 */ |
| #define ROGUE_CR_SLC3_SCRAMBLE3 0xE218U |
| #define ROGUE_CR_SLC3_SCRAMBLE3_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_SCRAMBLE3_BITS_SHIFT 0U |
| #define ROGUE_CR_SLC3_SCRAMBLE3_BITS_CLRMSK 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_SLC3_SCRAMBLE4 */ |
| #define ROGUE_CR_SLC3_SCRAMBLE4 0xE260U |
| #define ROGUE_CR_SLC3_SCRAMBLE4_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_SCRAMBLE4_BITS_SHIFT 0U |
| #define ROGUE_CR_SLC3_SCRAMBLE4_BITS_CLRMSK 0x0000000000000000ULL |
| |
| /* Register ROGUE_CR_SLC3_STATUS */ |
| #define ROGUE_CR_SLC3_STATUS 0xE220U |
| #define ROGUE_CR_SLC3_STATUS_MASKFULL 0xFFFFFFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_STATUS_WRITES1_SHIFT 48U |
| #define ROGUE_CR_SLC3_STATUS_WRITES1_CLRMSK 0x0000FFFFFFFFFFFFULL |
| #define ROGUE_CR_SLC3_STATUS_WRITES0_SHIFT 32U |
| #define ROGUE_CR_SLC3_STATUS_WRITES0_CLRMSK 0xFFFF0000FFFFFFFFULL |
| #define ROGUE_CR_SLC3_STATUS_READS1_SHIFT 16U |
| #define ROGUE_CR_SLC3_STATUS_READS1_CLRMSK 0xFFFFFFFF0000FFFFULL |
| #define ROGUE_CR_SLC3_STATUS_READS0_SHIFT 0U |
| #define ROGUE_CR_SLC3_STATUS_READS0_CLRMSK 0xFFFFFFFFFFFF0000ULL |
| |
| /* Register ROGUE_CR_SLC3_IDLE */ |
| #define ROGUE_CR_SLC3_IDLE 0xE228U |
| #define ROGUE_CR_SLC3_IDLE_MASKFULL 0x00000000000FFFFFULL |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_SHIFT 18U |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST2_CLRMSK 0xFFF3FFFFU |
| #define ROGUE_CR_SLC3_IDLE_MMU_SHIFT 17U |
| #define ROGUE_CR_SLC3_IDLE_MMU_CLRMSK 0xFFFDFFFFU |
| #define ROGUE_CR_SLC3_IDLE_MMU_EN 0x00020000U |
| #define ROGUE_CR_SLC3_IDLE_RDI_SHIFT 16U |
| #define ROGUE_CR_SLC3_IDLE_RDI_CLRMSK 0xFFFEFFFFU |
| #define ROGUE_CR_SLC3_IDLE_RDI_EN 0x00010000U |
| #define ROGUE_CR_SLC3_IDLE_IMGBV4_SHIFT 12U |
| #define ROGUE_CR_SLC3_IDLE_IMGBV4_CLRMSK 0xFFFF0FFFU |
| #define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_SHIFT 4U |
| #define ROGUE_CR_SLC3_IDLE_CACHE_BANKS_CLRMSK 0xFFFFF00FU |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_SHIFT 2U |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_DUST_CLRMSK 0xFFFFFFF3U |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_SHIFT 1U |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SLC3_IDLE_ORDERQ_JONES_EN 0x00000002U |
| #define ROGUE_CR_SLC3_IDLE_XBAR_SHIFT 0U |
| #define ROGUE_CR_SLC3_IDLE_XBAR_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SLC3_IDLE_XBAR_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SLC3_FAULT_STOP_STATUS */ |
| #define ROGUE_CR_SLC3_FAULT_STOP_STATUS 0xE248U |
| #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_MASKFULL 0x0000000000001FFFULL |
| #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_SHIFT 0U |
| #define ROGUE_CR_SLC3_FAULT_STOP_STATUS_BIF_CLRMSK 0xFFFFE000U |
| |
| /* Register ROGUE_CR_VDM_CONTEXT_STORE_MODE */ |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE 0xF048U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MASKFULL 0x0000000000000003ULL |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_SHIFT 0U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_CLRMSK 0xFFFFFFFCU |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INDEX 0x00000000U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_INSTANCE 0x00000001U |
| #define ROGUE_CR_VDM_CONTEXT_STORE_MODE_MODE_LIST 0x00000002U |
| |
| /* Register ROGUE_CR_CONTEXT_MAPPING0 */ |
| #define ROGUE_CR_CONTEXT_MAPPING0 0xF078U |
| #define ROGUE_CR_CONTEXT_MAPPING0_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING0_2D_SHIFT 24U |
| #define ROGUE_CR_CONTEXT_MAPPING0_2D_CLRMSK 0x00FFFFFFU |
| #define ROGUE_CR_CONTEXT_MAPPING0_CDM_SHIFT 16U |
| #define ROGUE_CR_CONTEXT_MAPPING0_CDM_CLRMSK 0xFF00FFFFU |
| #define ROGUE_CR_CONTEXT_MAPPING0_3D_SHIFT 8U |
| #define ROGUE_CR_CONTEXT_MAPPING0_3D_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_CONTEXT_MAPPING0_TA_SHIFT 0U |
| #define ROGUE_CR_CONTEXT_MAPPING0_TA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_CONTEXT_MAPPING1 */ |
| #define ROGUE_CR_CONTEXT_MAPPING1 0xF080U |
| #define ROGUE_CR_CONTEXT_MAPPING1_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING1_HOST_SHIFT 8U |
| #define ROGUE_CR_CONTEXT_MAPPING1_HOST_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_CONTEXT_MAPPING1_TLA_SHIFT 0U |
| #define ROGUE_CR_CONTEXT_MAPPING1_TLA_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_CONTEXT_MAPPING2 */ |
| #define ROGUE_CR_CONTEXT_MAPPING2 0xF088U |
| #define ROGUE_CR_CONTEXT_MAPPING2_MASKFULL 0x0000000000FFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_SHIFT 16U |
| #define ROGUE_CR_CONTEXT_MAPPING2_ALIST0_CLRMSK 0xFF00FFFFU |
| #define ROGUE_CR_CONTEXT_MAPPING2_TE0_SHIFT 8U |
| #define ROGUE_CR_CONTEXT_MAPPING2_TE0_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_CONTEXT_MAPPING2_VCE0_SHIFT 0U |
| #define ROGUE_CR_CONTEXT_MAPPING2_VCE0_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_CONTEXT_MAPPING3 */ |
| #define ROGUE_CR_CONTEXT_MAPPING3 0xF090U |
| #define ROGUE_CR_CONTEXT_MAPPING3_MASKFULL 0x0000000000FFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_SHIFT 16U |
| #define ROGUE_CR_CONTEXT_MAPPING3_ALIST1_CLRMSK 0xFF00FFFFU |
| #define ROGUE_CR_CONTEXT_MAPPING3_TE1_SHIFT 8U |
| #define ROGUE_CR_CONTEXT_MAPPING3_TE1_CLRMSK 0xFFFF00FFU |
| #define ROGUE_CR_CONTEXT_MAPPING3_VCE1_SHIFT 0U |
| #define ROGUE_CR_CONTEXT_MAPPING3_VCE1_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_BIF_JONES_OUTSTANDING_READ */ |
| #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ 0xF098U |
| #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_SHIFT 0U |
| #define ROGUE_CR_BIF_JONES_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ */ |
| #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ 0xF0A0U |
| #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_SHIFT 0U |
| #define ROGUE_CR_BIF_BLACKPEARL_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_BIF_DUST_OUTSTANDING_READ */ |
| #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ 0xF0A8U |
| #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_MASKFULL 0x000000000000FFFFULL |
| #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_SHIFT 0U |
| #define ROGUE_CR_BIF_DUST_OUTSTANDING_READ_COUNTER_CLRMSK 0xFFFF0000U |
| |
| /* Register ROGUE_CR_CONTEXT_MAPPING4 */ |
| #define ROGUE_CR_CONTEXT_MAPPING4 0xF210U |
| #define ROGUE_CR_CONTEXT_MAPPING4_MASKFULL 0x0000FFFFFFFFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_SHIFT 40U |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_MMU_STACK_CLRMSK 0xFFFF00FFFFFFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_SHIFT 32U |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_UFSTACK_CLRMSK 0xFFFFFF00FFFFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_SHIFT 24U |
| #define ROGUE_CR_CONTEXT_MAPPING4_3D_FSTACK_CLRMSK 0xFFFFFFFF00FFFFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_SHIFT 16U |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_MMU_STACK_CLRMSK 0xFFFFFFFFFF00FFFFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_SHIFT 8U |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_UFSTACK_CLRMSK 0xFFFFFFFFFFFF00FFULL |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_SHIFT 0U |
| #define ROGUE_CR_CONTEXT_MAPPING4_TA_FSTACK_CLRMSK 0xFFFFFFFFFFFFFF00ULL |
| |
| /* Register ROGUE_CR_MULTICORE_GPU */ |
| #define ROGUE_CR_MULTICORE_GPU 0xF300U |
| #define ROGUE_CR_MULTICORE_GPU_MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_SHIFT 6U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_FRAGMENT_EN 0x00000040U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_SHIFT 5U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_GEOMETRY_EN 0x00000020U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_SHIFT 4U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_COMPUTE_EN 0x00000010U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_SHIFT 3U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_MULTICORE_GPU_CAPABILITY_PRIMARY_EN 0x00000008U |
| #define ROGUE_CR_MULTICORE_GPU_ID_SHIFT 0U |
| #define ROGUE_CR_MULTICORE_GPU_ID_CLRMSK 0xFFFFFFF8U |
| |
| /* Register ROGUE_CR_MULTICORE_SYSTEM */ |
| #define ROGUE_CR_MULTICORE_SYSTEM 0xF308U |
| #define ROGUE_CR_MULTICORE_SYSTEM_MASKFULL 0x000000000000000FULL |
| #define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_SHIFT 0U |
| #define ROGUE_CR_MULTICORE_SYSTEM_GPU_COUNT_CLRMSK 0xFFFFFFF0U |
| |
| /* Register ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON */ |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON 0xF310U |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MULTICORE_FRAGMENT_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON */ |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON 0xF320U |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MULTICORE_GEOMETRY_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON */ |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON 0xF330U |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_MASKFULL 0x00000000FFFFFFFFULL |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_SHIFT 30U |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_TYPE_CLRMSK 0x3FFFFFFFU |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_SHIFT 8U |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_WORKLOAD_EXECUTE_COUNT_CLRMSK 0xC00000FFU |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_SHIFT 0U |
| #define ROGUE_CR_MULTICORE_COMPUTE_CTRL_COMMON_GPU_ENABLE_CLRMSK 0xFFFFFF00U |
| |
| /* Register ROGUE_CR_ECC_RAM_ERR_INJ */ |
| #define ROGUE_CR_ECC_RAM_ERR_INJ 0xF340U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_SHIFT 4U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_SLC_SIDEKICK_EN 0x00000010U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_SHIFT 3U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_USC_EN 0x00000008U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_SHIFT 2U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_TPU_MCU_L0_EN 0x00000004U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_SHIFT 1U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_RASCAL_EN 0x00000002U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_SHIFT 0U |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_ECC_RAM_ERR_INJ_MARS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_ECC_RAM_INIT_KICK */ |
| #define ROGUE_CR_ECC_RAM_INIT_KICK 0xF348U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_SHIFT 4U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_SLC_SIDEKICK_EN 0x00000010U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_SHIFT 3U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_USC_EN 0x00000008U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_SHIFT 2U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_TPU_MCU_L0_EN 0x00000004U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_SHIFT 1U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_RASCAL_EN 0x00000002U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_SHIFT 0U |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_ECC_RAM_INIT_KICK_MARS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_ECC_RAM_INIT_DONE */ |
| #define ROGUE_CR_ECC_RAM_INIT_DONE 0xF350U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_MASKFULL 0x000000000000001FULL |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_SHIFT 4U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_SLC_SIDEKICK_EN 0x00000010U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_SHIFT 3U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_USC_EN 0x00000008U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_SHIFT 2U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_TPU_MCU_L0_EN 0x00000004U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_SHIFT 1U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_RASCAL_EN 0x00000002U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_SHIFT 0U |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_ECC_RAM_INIT_DONE_MARS_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SAFETY_EVENT_ENABLE */ |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE 0xF390U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SAFETY_EVENT_STATUS */ |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE 0xF398U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_SHIFT 3U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__TRP_FAIL_EN 0x00000008U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_SHIFT 2U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_FW_EN 0x00000004U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_SHIFT 1U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__FAULT_GPU_EN 0x00000002U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SAFETY_EVENT_STATUS__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_SAFETY_EVENT_CLEAR */ |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE 0xF3A0U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_SHIFT 3U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__TRP_FAIL_EN 0x00000008U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_SHIFT 2U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_FW_EN 0x00000004U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_SHIFT 1U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__FAULT_GPU_EN 0x00000002U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_SAFETY_EVENT_CLEAR__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U |
| |
| /* Register ROGUE_CR_MTS_SAFETY_EVENT_ENABLE */ |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE 0xF3D8U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__MASKFULL 0x000000000000007FULL |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_SHIFT 6U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_CLRMSK 0xFFFFFFBFU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__CPU_PAGE_FAULT_EN 0x00000040U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_SHIFT 5U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_CLRMSK 0xFFFFFFDFU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__SAFE_COMPUTE_FAIL_EN 0x00000020U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_SHIFT 4U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_CLRMSK 0xFFFFFFEFU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__WATCHDOG_TIMEOUT_EN 0x00000010U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_SHIFT 3U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_CLRMSK 0xFFFFFFF7U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__TRP_FAIL_EN 0x00000008U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_SHIFT 2U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_CLRMSK 0xFFFFFFFBU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_FW_EN 0x00000004U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_SHIFT 1U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_CLRMSK 0xFFFFFFFDU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__FAULT_GPU_EN 0x00000002U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_SHIFT 0U |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_CLRMSK 0xFFFFFFFEU |
| #define ROGUE_CR_MTS_SAFETY_EVENT_ENABLE__ROGUEXE__GPU_PAGE_FAULT_EN 0x00000001U |
| |
| /* clang-format on */ |
| |
| #endif /* PVR_ROGUE_CR_DEFS_H */ |
